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/Documentation/driver-api/usb/
Ddwc3.rst202 ``ep[0..15]{in,out}/``
237 ``ep[0..15]{in,out}``
275 000000002c754000,481,normal,1,0,1,0,0,0
276 000000002c75c000,481,normal,1,0,1,0,0,0
277 000000002c780000,481,normal,1,0,1,0,0,0
278 000000002c788000,481,normal,1,0,1,0,0,0
279 000000002c78c000,481,normal,1,0,1,0,0,0
280 000000002c754000,481,normal,1,0,1,0,0,0
281 000000002c75c000,481,normal,1,0,1,0,0,0
282 000000002c784000,481,normal,1,0,1,0,0,0
[all …]
/Documentation/networking/device_drivers/qlogic/
Dqlge.rst25 return sizeof(Object(prog, struct_str, address=0x0))
45 .base_cq = (u8)0,
52 .flags = (unsigned long)0,
53 .wol = (u32)0,
55 .tx_pkts = (u64)0,
56 .tx_bytes = (u64)0,
57 .tx_mcast_pkts = (u64)0,
58 .tx_bcast_pkts = (u64)0,
59 .tx_ucast_pkts = (u64)0,
60 .tx_ctl_pkts = (u64)0,
[all …]
/Documentation/tools/rtla/
Drtla-timerlat-hist.rst37 in the cpus *0-4*, *skipping zero* only lines. Moreover, **rtla timerlat
43 [root@alien ~]# timerlat hist -d 10m -c 0-4 -P d:100us:1ms -p 1000 --no-aa
46 # Duration: 0 00:10:00
48 …0 276489 0 206089 0 466018 0 481102 0 205546 …
62 …14 1 88 1 116 15 198 42 223 0 …
63 …15 2 63 3 94 11 139 20 150 0 …
64 …16 2 37 0 56 5 78 10 102 0 …
65 …17 0 18 0 28 4 57 8 80 0 …
66 …18 0 8 0 17 2 50 6 56 0 …
67 …19 0 9 0 5 0 19 0 48 0 …
[all …]
/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
Dcdns,cdns-pcie-host.yaml47 bus-range = <0x0 0xff>;
48 linux,pci-domain = <0>;
49 vendor-id = <0x17cd>;
50 device-id = <0x0200>;
52 reg = <0x0 0xfb000000 0x0 0x01000000>,
53 <0x0 0x41000000 0x0 0x00001000>;
56 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
57 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
58 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
60 #interrupt-cells = <0x1>;
[all …]
Dxgene-pci.txt35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
Dxilinx-versal-cpm.yaml53 const: 0
84 interrupts = <0 72 4>;
86 interrupt-map-mask = <0 0 0 7>;
87 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
88 <0 0 0 2 &pcie_intc_0 1>,
89 <0 0 0 3 &pcie_intc_0 2>,
90 <0 0 0 4 &pcie_intc_0 3>;
91 bus-range = <0x00 0xff>;
92 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
93 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
Dmediatek-pcie.txt32 where N starting from 0 to one less than the number of root ports.
80 reg = <0 0x1a000000 0 0x1000>;
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
Dhisilicon,kirin-pcie.yaml77 reg = <0x0 0xf4000000 0x0 0x1000>,
78 <0x0 0xff3fe000 0x0 0x1000>,
79 <0x0 0xf3f20000 0x0 0x40000>,
80 <0x0 0xf5000000 0x0 0x2000>;
82 bus-range = <0x0 0xff>;
86 ranges = <0x02000000 0x0 0x00000000
87 0x0 0xf6000000
88 0x0 0x02000000>;
91 interrupts = <0 283 4>;
93 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
22 pixel_order 0x0006 8
23 - e GRBG 0
27 MIPI_CCS_version 0x0007 8
28 - e v1_0 0x10
29 - e v1_1 0x11
31 - f minor 0 3
32 data_pedestal 0x0008 16
[all …]
/Documentation/userspace-api/media/v4l/
Dcrop.svg9 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
17 viewBox="0 0 739.11388 339.6584"
25 …d="m 0,0 0,1895 4118,0 L 4118,0 0,0 Z m 3051.62,250.48 8.19,17.01 -46.93,23.31 29.61,-25.515 -38.1…
27 inkscape:connector-curvature="0"
31 …0,0 0,1895 4118,0 0,-1626 -1,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 …
32 …0 0,1 -1,0 0,1 -1,0 0,1 -2,0 0,1 -1,0 0,2 2,0 0,-1 4,0 0,-1 5,0 0,-1 4,0 0,-1 5,0 0,-1 5,0 0,-1 4,…
34 inkscape:connector-curvature="0"
38 …0,0 0,1895 4118,0 0,-136 -3,0 0,-1 -11,0 0,-1 -11,0 0,-1 -11,0 0,-1 -11,0 0,-1 5,0 0,-1 6,0 0,-1 7…
40 inkscape:connector-curvature="0"
44 …d="m 0,0 0,1895 4118,0 L 4118,0 0,0 Z m 3056.98,1740.43 -1.58,18.9 -52.6,-4.72 38.74,-6.3 -36.85,-…
[all …]
/Documentation/ABI/testing/
Dsysfs-bus-event_source-devices-dfl_fme13 event = "config:0-11" - event ID
19 fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff"
21 It shows this fab_mmio_read is a fabric type (0x02) event with
22 0x06 local event id for overall monitoring (portid=0xff).
43 Basic events (evtype=0x00)::
45 clock = "event=0x00,evtype=0x00,portid=0xff"
47 Cache events (evtype=0x01)::
49 cache_read_hit = "event=0x00,evtype=0x01,portid=0xff"
50 cache_read_miss = "event=0x01,evtype=0x01,portid=0xff"
51 cache_write_hit = "event=0x02,evtype=0x01,portid=0xff"
[all …]
/Documentation/devicetree/bindings/input/
Dti,nspire-keypad.txt29 reg = <0x900E0000 0x1000>;
38 0x0000001c 0x0001001c 0x00040039
39 0x0005002c 0x00060015 0x0007000b
40 0x0008000f 0x0100002d 0x01010011
41 0x0102002f 0x01030004 0x01040016
42 0x01050014 0x0106001f 0x01070002
43 0x010a006a 0x02000013 0x02010010
44 0x02020019 0x02030007 0x02040018
45 0x02050031 0x02060032 0x02070005
46 0x02080028 0x0209006c 0x03000026
[all …]
Ddlg,da7280.txt25 device enabled by sending magnitude (X > 0),
31 Valid values: 0 - 6000000.
33 Valid values: 0 - 6000000.
35 Valid values: 0 - 252000.
38 Valid values: 0 - 1500000000.
49 Valid range: 0 - 15.
52 Valid range: 0 - 15.
54 when gpi0 is triggered, 'N' must be 0 - 2.
55 Valid range: 0 - 15.
57 "Single-pattern" or "Multi-pattern", 'N' must be 0 - 2.
[all …]
Dgoogle,cros-ec-keyb.yaml43 (((row) & 0xFF) << 24) | (((column) & 0xFF) << 16)
77 MATRIX_KEY(0x00, 0x02, 0) /* T1 */
78 MATRIX_KEY(0x03, 0x02, 0) /* T2 */
79 MATRIX_KEY(0x02, 0x02, 0) /* T3 */
80 MATRIX_KEY(0x01, 0x02, 0) /* T4 */
81 MATRIX_KEY(0x03, 0x04, 0) /* T5 */
82 MATRIX_KEY(0x02, 0x04, 0) /* T6 */
83 MATRIX_KEY(0x01, 0x04, 0) /* T7 */
84 MATRIX_KEY(0x02, 0x09, 0) /* T8 */
85 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
[all …]
/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/Documentation/mm/
Dzsmalloc.rst9 (0-order) pages, it would suffer from very high fragmentation --
13 To overcome these issues, zsmalloc allocates a bunch of 0-order pages
15 pages act as a single higher-order page i.e. an object can span 0-order
45 …30 512 0 12 4 1 0 1 0 0 1…
46 …28 2 7 2 2 1 0 1 0 0 …
47 … 6 3 4 1 2 1 0 0 0 1 …
85 the number of 0-order pages to make a zspage
99 Each zspage can contain up to ZSMALLOC_CHAIN_SIZE physical (0-order) pages.
111 94 1536 0 .... 0 0 0 0 3 0
112 100 1632 0 .... 0 0 0 0 2 0
[all …]
/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/Documentation/devicetree/bindings/net/
Dmdio-mux-gpio.yaml44 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
47 #size-cells = <0>;
52 #size-cells = <0>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
57 <3 0x11 0 0x00aa>,
58 <3 0x12 0 0x4105>,
59 <3 0x13 0 0x0a60>;
65 marvell,reg-init = <3 0x10 0 0x5777>,
66 <3 0x11 0 0x00aa>,
67 <3 0x12 0 0x4105>,
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Dpincfg.txt7 - port : port number of the pin; 0-6 represent port A-G in UM.
11 0 = The pin is disabled
18 0 = The pin is actively driven as an output
32 0 3 1 0 1 0 /* TxD0 */
33 0 4 1 0 1 0 /* TxD1 */
34 0 5 1 0 1 0 /* TxD2 */
35 0 6 1 0 1 0 /* TxD3 */
36 1 6 1 0 3 0 /* TxD4 */
37 1 7 1 0 1 0 /* TxD5 */
38 1 9 1 0 2 0 /* TxD6 */
[all …]

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