Searched +full:0 +full:x100 (Results 1 – 25 of 400) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | mscc,vsc7514-switch.yaml | 38 "^port@[0-9a-f]+$":
55 "^port@[0-9a-f]+$":
142 reg = <0x1010000 0x10000>,
143 <0x1030000 0x10000>,
144 <0x1080000 0x100>,
145 <0x10e0000 0x10000>,
146 <0x11e0000 0x100>,
147 <0x11f0000 0x100>,
148 <0x1200000 0x100>,
149 <0x1210000 0x100>,
[all …]
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| D | faraday,ftmac.txt | 16 reg = <0x90900000 0x100>;
17 interrupts = <25 0>;
22 reg = <0x92000000 0x100>;
23 interrupts = <27 0>;
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,pru-rproc.yaml | 19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
79 pattern: "^rtu@[0-9a-f]+$"
91 pattern: "^txpru@[0-9a-f]+"
95 pattern: "^pru@[0-9a-f]+$"
108 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
112 ranges = <0x0 0x300000 0x80000>;
114 pruss: pruss@0 {
116 reg = <0x0 0x80000>;
[all …]
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| /Documentation/devicetree/bindings/mmc/ |
| D | litex,mmc.yaml | 69 reg = <0x12005000 0x100>,
70 <0x12003800 0x100>,
71 <0x12003000 0x100>,
72 <0x12004800 0x100>,
73 <0x12004000 0x100>;
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| D | aspeed,sdhci.yaml | 42 "^sdhci@[0-9a-f]+$":
86 reg = <0x1e740000 0x100>;
89 ranges = <0 0x1e740000 0x20000>;
94 reg = <0x100 0x100>;
102 reg = <0x200 0x100>;
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| /Documentation/devicetree/bindings/media/ |
| D | nvidia,tegra-vde.yaml | 97 reg = <0x6001a000 0x1000>, /* Syntax Engine */
98 <0x6001b000 0x1000>, /* Video Bitstream Engine */
99 <0x6001c000 0x100>, /* Macroblock Engine */
100 <0x6001c200 0x100>, /* Post-processing Engine */
101 <0x6001c400 0x100>, /* Motion Compensation Engine */
102 <0x6001c600 0x100>, /* Transform Engine */
103 <0x6001c800 0x100>, /* Pixel prediction block */
104 <0x6001ca00 0x100>, /* Video DMA */
105 <0x6001d800 0x300>; /* Video frame controls */
109 interrupts = <0 9 4>, /* Sync token */
[all …]
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-pxa-pci-ce4100.txt | 39 reg = <0x15a00 0x0 0x0 0x0 0x0>;
48 ranges = <0 0 0x02000000 0 0xdffe0500 0x100
49 1 0 0x02000000 0 0xdffe0600 0x100
50 2 0 0x02000000 0 0xdffe0700 0x100>;
52 i2c@0 {
54 #size-cells = <0>;
60 reg = <0 0 0x100>;
67 #size-cells = <0>;
69 reg = <1 0 0x100>;
75 reg = <0x26>;
[all …]
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| D | i2c-pnx.txt | 9 - #size-cells: always 0
19 reg = <0x400a0000 0x100>;
21 interrupts = <51 0>;
23 #size-cells = <0>;
28 reg = <0x400a8000 0x100>;
30 interrupts = <50 0>;
32 #size-cells = <0>;
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| /Documentation/devicetree/bindings/phy/ |
| D | brcm,stingray-usb-phy.txt | 10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
16 usbphy0: usb-phy@0 {
18 reg = <0x00000000 0x100>;
24 reg = <0x00010000 0x100>,
30 reg = <0x00020000 0x100>,
31 #phy-cells = <0>;
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| D | phy-miphy365x.txt | 43 st,syscfg = <&syscfg_rear 0x824 0x828>;
49 reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
56 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
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| /Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-dfll.txt | 32 - #clock-cells: Must be 0.
67 - pinctrl-0: I/O pad configuration when PWM control is enabled.
77 reg = <0 0x70110000 0 0x100>, /* DFLL control */
78 <0 0x70110000 0 0x100>, /* I2C output control */
79 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
80 <0 0x70110200 0 0x100>; /* Look-up table RAM */
88 #clock-cells = <0>;
93 nvidia,droop-ctrl = <0x00000f00>;
96 nvidia,ci = <0>;
106 reg = <0 0x70110000 0 0x100>, /* DFLL control */
[all …]
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| D | zynq-7000.txt | 17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
27 Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
41 0: armpll
95 reg = <0x100 0x100>;
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 25 reg = <0x11800 0x6f000000 0x0 0x100>;
36 reg = <0x16f00 0x00000000 0x0 0x100>;
37 interrupts = <0 56>;
42 reg = <0x16f00 0x00000400 0x0 0x100>;
43 interrupts = <0 56>;
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| /Documentation/devicetree/bindings/dma/ |
| D | altr,msgdma.yaml | 43 The cell identifies the channel id (must be 0)
59 reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
61 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
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| D | mv-xor.txt | 30 reg = <0xd0060900 0x100
31 0xd0060b00 0x100>;
32 clocks = <&coreclk 0>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | mpc8xxx-wdt.txt | 10 On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
11 On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
12 On the 8xx, "General System Interface Unit" area: <0x0 0x10>
17 On the 83xx, it is located at offset 0x910
18 On the 86xx, it is located at offset 0xe0094
19 On the 8xx, it is located at offset 0x288
22 WDT: watchdog@0 {
24 reg = <0x0 0x10 0x288 0x4>;
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| D | mediatek,mt7621-wdt.yaml | 38 reg = <0x100 0x100>;
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| /Documentation/devicetree/bindings/pci/ |
| D | mediatek,mt7621-pcie.yaml | 26 - description: pcie port 0 RC control registers
34 '^pcie@[0-2],0$':
49 pattern: '^pcie-phy[0-2]$'
81 reg = <0x1e140000 0x100>,
82 <0x1e142000 0x100>,
83 <0x1e143000 0x100>,
84 <0x1e144000 0x100>;
89 pinctrl-0 = <&pcie_pins>;
91 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
92 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
[all …]
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-timer.txt | 22 reg = <0x41100 0x100 0x41300 4>;
24 /* Another AMP partition is using timers 0 and 1 */
27 interrupts = <2 0 3 0
28 3 0 3 0>;
33 reg = <0x42100 0x100 0x42300 4>;
34 interrupts = <4 0 3 0
35 5 0 3 0
36 6 0 3 0
37 7 0 3 0>;
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,scu.yaml | 14 with a Snoop Control Unit. The register range is usually 256 (0x100)
45 reg = <0xa0410000 0x100>;
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| /Documentation/devicetree/bindings/perf/ |
| D | amlogic,g12-ddr-pmu.yaml | 50 reg = <0x0 0xff638000 0x0 0x100>,
51 <0x0 0xff638c00 0x0 0x100>;
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| /Documentation/devicetree/bindings/nvmem/layouts/ |
| D | fixed-layout.yaml | 49 reg = <0x100 0x6>;
55 reg = <0x110 0x11>;
60 reg = <0x4000 0x100>;
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 40 reg = <0xffd08140 0x4>;
41 interrupts = <0 36 1>, <0 37 1>;
46 reg = <0xffd08144 0x4>;
48 interrupts = <0 178 1>, <0 179 1>;
141 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 IRQ_TYPE_LEVEL_HIGH>;
149 reg = <0xffd06010 0x4>;
150 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
156 reg = <0xff8c3000 0x90>;
163 reg = <0xff8c0800 0x400>;
[all …]
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| /Documentation/devicetree/bindings/virtio/ |
| D | mmio.yaml | 52 reg = <0x3000 0x100>;
61 reg = <0x3100 0x100>;
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| /Documentation/devicetree/bindings/mfd/ |
| D | samsung,exynos5433-lpass.yaml | 40 "^dma-controller@[0-9a-f]+$":
43 "^i2s@[0-9a-f]+$":
46 "^serial@[0-9a-f]+$":
67 reg = <0x11400000 0x100>, <0x11500000 0x08>;
77 reg = <0x11420000 0x1000>;
89 reg = <0x11440000 0x100>;
90 dmas = <&adma 0>, <&adma 2>;
94 #size-cells = <0>;
101 pinctrl-0 = <&i2s0_bus>;
108 reg = <0x11460000 0x100>;
[all …]
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