Searched +full:0 +full:x10000 (Results 1 – 25 of 341) sorted by relevance
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| /Documentation/devicetree/bindings/crypto/ |
| D | hisilicon,hip07-sec.txt | 9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,j721e-dss.yaml | 27 - description: common_s0 DSS Shared common 0
91 - description: common_s0 DSS Shared common 0
113 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
165 <0x04a50000 0x10000>, /* vid1 */
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | mscc,vsc7514-switch.yaml | 38 "^port@[0-9a-f]+$":
55 "^port@[0-9a-f]+$":
142 reg = <0x1010000 0x10000>,
143 <0x1030000 0x10000>,
144 <0x1080000 0x100>,
145 <0x10e0000 0x10000>,
146 <0x11e0000 0x100>,
147 <0x11f0000 0x100>,
148 <0x1200000 0x100>,
149 <0x1210000 0x100>,
[all …]
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| D | hisilicon-hip04-net.txt | 43 reg = <0x28f1000 0x1000>;
45 #size-cells = <0>;
47 phy0: ethernet-phy@0 {
49 reg = <0>;
50 marvell,reg-init = <18 0x14 0 0x8001>;
56 marvell,reg-init = <18 0x14 0 0x8001>;
62 reg = <0x28c0000 0x10000>;
67 reg = <0x28b0000 0x10000>;
68 interrupts = <0 413 4>;
70 port-handle = <&ppe 31 0 31>;
[all …]
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| D | socionext,synquacer-netsec.yaml | 55 reg = <0x522d0000 0x10000>, <0x10000000 0x10000>;
66 #size-cells = <0>;
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| /Documentation/devicetree/bindings/mtd/partitions/ |
| D | brcm,bcm963xx-imagetag.txt | 18 reg = <0x1e000000 0x2000000>;
26 cfe@0 {
27 reg = <0x0 0x10000>;
32 reg = <0x10000 0x7d0000>;
37 reg = <0x7e0000 0x10000>;
42 reg = <0x7f0000 0x10000>;
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 52 - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
71 reg = <0x11800 0x00000000 0x0 0x200>;
76 ranges = <0 0 0x0 0x1f400000 0xc00000>,
77 <1 0 0x10000 0x30000000 0>,
78 <2 0 0x10000 0x40000000 0>,
79 <3 0 0x10000 0x50000000 0>,
80 <4 0 0x0 0x1d020000 0x10000>,
81 <5 0 0x0 0x1d040000 0x10000>,
82 <6 0 0x0 0x1d050000 0x10000>,
83 <7 0 0x10000 0x90000000 0>;
[all …]
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| /Documentation/devicetree/bindings/mtd/ |
| D | mxicy,nand-ecc-engine.yaml | 36 reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
38 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
41 #size-cells = <0>;
43 flash@0 {
45 reg = <0>;
52 reg = <0x43c40000 0x10000>;
59 reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
61 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
64 #size-cells = <0>;
67 flash@0 {
[all …]
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| D | cadence-nand-controller.txt | 11 - #size-cells : should be 0.
27 - reg: shall contain the native Chip Select ids from 0 to max supported by
38 #size-cells = <0>;
39 reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
43 interrupts = <2 0>;
44 nand@0 {
45 reg = <0>;
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,rpmh-rsc.yaml | 78 enum: [ 0, 1, 2, 3 ]
97 - const: drv-0
115 '^regulators(-[0-9])?$':
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
145 reg = <0x179c0000 0x10000>,
[all …]
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| /Documentation/devicetree/bindings/usb/ |
| D | starfive,jh7110-usb.yaml | 68 "^usb@[0-9a-f]+$":
88 ranges = <0x0 0x10100000 0x100000>;
91 starfive,stg-syscon = <&stg_syscon 0x4>;
105 usb@0 {
107 reg = <0x0 0x10000>,
108 <0x10000 0x10000>,
109 <0x20000 0x10000>;
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| D | fsl,imx8qm-cdns3.yaml | 51 "^usb@[0-9a-f]+$":
74 reg = <0x5b110000 0x10000>;
90 reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */
91 <0x5b130000 0x10000>, /* memory area for HOST registers */
92 <0x5b140000 0x10000>; /* memory area for DEVICE registers */
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| D | cdns,usb3.yaml | 91 reg = <0x00 0x6000000 0x00 0x10000>,
92 <0x00 0x6010000 0x00 0x10000>,
93 <0x00 0x6020000 0x00 0x10000>;
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| D | ti,j721e-usb.yaml | 45 If present, it restricts the controller to USB2.0 mode of
88 reg = <0x00 0x4104000 0x00 0x100>;
99 reg = <0x00 0x6000000 0x00 0x10000>,
100 <0x00 0x6010000 0x00 0x10000>,
101 <0x00 0x6020000 0x00 0x10000>;
103 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
105 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra186-mc.yaml | 27 pattern: "^memory-controller@[0-9a-f]+$"
62 "^external-memory-controller@[0-9a-f]+$":
95 const: 0
244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
245 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
246 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
247 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
248 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
249 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
256 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | xlnx,i2s.txt | 19 reg = <0x0 0xa0080000 0x0 0x10000>;
20 xlnx,dwidth = <0x18>;
25 reg = <0x0 0xa0090000 0x0 0x10000>;
26 xlnx,dwidth = <0x18>;
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| /Documentation/devicetree/bindings/ata/ |
| D | cavium-compact-flash.txt | 24 compact-flash@5,0 {
26 reg = <5 0 0x10000>, <6 0 0x10000>;
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra186-display.yaml | 15 pattern: "^display-hub@[0-9a-f]+$"
45 - description: window group 0 reset
69 "^display@[0-9a-f]+$":
127 reg = <0x15200000 0x00040000>;
147 ranges = <0x15200000 0x15200000 0x40000>;
151 reg = <0x15200000 0x10000>;
165 nvidia,head = <0>;
170 reg = <0x15210000 0x10000>;
189 reg = <0x15220000 0x10000>;
216 reg = <0x15200000 0x00040000>;
[all …]
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mailbox.txt | 36 mboxes = <&mailbox 0 &mailbox 1>;
43 reg = <0x50000000 0x10000>;
47 ranges = <0 0x50000000 0x10000>;
49 cl_shmem: shmem@0 {
51 reg = <0x0 0x200>;
57 mboxes = <&mailbox 0>;
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| /Documentation/devicetree/bindings/virtio/ |
| D | pci-iommu.yaml | 40 BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be
63 reg = <0x0 0x40000000 0x0 0x1000000>;
64 ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;
70 iommu-map = <0x0 &iommu0 0x0 0x8
71 0x9 &iommu0 0x9 0xfff7>;
74 iommu0: iommu@1,0 {
76 reg = <0x800 0 0 0 0>;
85 reg = <0x0 0x50000000 0x0 0x1000000>;
86 ranges = <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0f000000>;
90 * with endpoint IDs 0x10000 - 0x1ffff
[all …]
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| /Documentation/devicetree/bindings/dma/ |
| D | apm-xgene-dma.txt | 27 clocks = <&socplldiv2 0>;
28 reg = <0x0 0x1f27c000 0x0 0x1000>;
36 reg = <0x0 0x1f270000 0x0 0x10000>,
37 <0x0 0x1f200000 0x0 0x10000>,
38 <0x0 0x1b000000 0x0 0x400000>,
39 <0x0 0x1054a000 0x0 0x100>;
40 interrupts = <0x0 0x82 0x4>,
41 <0x0 0xb8 0x4>,
42 <0x0 0xb9 0x4>,
43 <0x0 0xba 0x4>,
[all …]
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra186-pmc.yaml | 164 reg = <0x0c360000 0x10000>,
165 <0x0c370000 0x10000>,
166 <0x0c380000 0x10000>,
167 <0x0c390000 0x10000>;
184 reg = <0x03400000 0x10000>;
196 pinctrl-0 = <&sdmmc1_3v3>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-mpc8xxx.txt | 12 0 = active high
24 reg = <0x1100 0x080>;
25 interrupts = <78 0x8>;
32 reg = <0x0 0x2300000 0x0 0x10000>;
33 interrupts = <0 36 0x4>; /* Level high type */
46 reg = <0x0 0x2300000 0x0 0x10000>;
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| /Documentation/devicetree/bindings/pci/ |
| D | pci-armada8k.txt | 32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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| /Documentation/devicetree/bindings/media/ |
| D | nxp,imx8mq-vpu.yaml | 53 reg = <0x38300000 0x10000>;
65 reg = <0x38310000 0x10000>;
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