Searched +full:0 +full:x20 (Results 1 – 25 of 220) sorted by relevance
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| /Documentation/i2c/ |
| D | i2c-address-translators.rst | 40 Slave X @ 0x10
46 Slave Y @ 0x10
62 X (bus B, 0x10) 0x20
63 Y (bus C, 0x10) 0x30
68 - Slave X driver requests a transaction (on adapter B), slave address 0x10
69 - ATR driver finds slave X is on bus B and has alias 0x20, rewrites
70 messages with address 0x20, forwards to adapter A
71 - Physical I2C transaction on bus A, slave address 0x20
72 - ATR chip detects transaction on address 0x20, finds it in table,
73 propagates transaction on bus B with address translated to 0x10,
[all …]
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp55xx.yaml | 42 - 0 # automode
58 - 0 # D1~9 are connected to VDD
67 const: 0
78 '^multi-led@[0-8]$':
91 const: 0
94 "^led@[0-8]$":
103 Current setting at each LED channel (mA x10, 0 if LED is not connected)
104 minimum: 0
117 "^led@[0-8]$":
126 Current setting at each LED channel (mA x10, 0 if LED is not connected)
[all …]
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| /Documentation/devicetree/bindings/power/ |
| D | rockchip,power-controller.yaml | 54 const: 0
63 "^power-domain@[0-9a-f]+$":
74 const: 0
77 "^power-domain@[0-9a-f]+$":
88 const: 0
91 "^power-domain@[0-9a-f]+$":
99 const: 0
143 enum: [0, 1]
145 Must be 0 for nodes representing a single PM domain and 1 for nodes
163 reg = <0x0 0xffa90000 0x0 0x20>;
[all …]
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| D | pd-samsung.yaml | 42 const: 0
58 reg = <0x10023c80 0x20>;
59 #power-domain-cells = <0>;
65 reg = <0x10044060 0x20>;
66 #power-domain-cells = <0>;
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| /Documentation/devicetree/bindings/clock/ |
| D | lsi,axm5516-clks.txt | 18 reg = <0x20 0x10020000 0 0x20000>;
23 reg = <0x20 0x10080000 0 0x1000>;
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| D | ti-clkctrl.txt | 34 cm_l4per@0 {
38 reg = <0x20 0x1b0>;
47 #define OMAP4_CLKCTRL_OFFSET 0x20
52 #define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28)
53 #define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30)
54 #define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38)
56 #define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60)
61 clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.yaml | 46 - "smc" : SMC #0, following the SMCCC
47 - "hvc" : HVC #0, following the SMCCC
72 '^mailbox@[0-9a-f]+$':
85 It contains tx(0) or rx(1) channel IPI id number.
116 #address-cells = <0x2>;
117 #size-cells = <0x2>;
121 xlnx,ipi-id = <0>;
127 reg = <0x0 0xff9905c0 0x0 0x20>,
128 <0x0 0xff9905e0 0x0 0x20>,
129 <0x0 0xff990e80 0x0 0x20>,
[all …]
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| /Documentation/devicetree/bindings/pci/ |
| D | sifive,fu740-pcie.yaml | 94 reg = <0xe 0x00000000 0x0 0x80000000>,
95 <0xd 0xf0000000 0x0 0x10000000>,
96 <0x0 0x100d0000 0x0 0x1000>;
100 bus-range = <0x0 0xff>;
101 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
102 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
103 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
104 … <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
105 num-lanes = <0x8>;
109 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
[all …]
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| D | layerscape-pci.txt | 44 The second entry is the physical PCIe controller index starting from '0'.
58 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
59 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
61 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
68 bus-range = <0x0 0xff>;
69 … ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
70 … 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
73 interrupt-map-mask = <0 0 0 7>;
74 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
75 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /Documentation/devicetree/bindings/ |
| D | resource-names.txt | 27 ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
28 <1 0 0x49000000 0x00001000>; /* L3 path */
31 reg = <0 0x10 0x10>, <0 0x20 0x10>,
32 <1 0x10 0x10>, <1 0x20 0x10>;
41 reg = <0 0x40 0x10>, <1 0x40 0x10>;
49 reg = <0x4a064000 0x800>, <0x4a064800 0x200>,
50 <0x4a064c00 0x200>;
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | cypress,cy8ctma140.yaml | 20 const: 0x20
58 #size-cells = <0>;
61 reg = <0x20>;
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| /Documentation/leds/ |
| D | leds-mlxcpld.rst | 28 - CPLD reg offset: 0x20
29 - Bits [3:0]
32 - CPLD reg offset: 0x20
36 - CPLD reg offset: 0x21
37 - Bits [3:0]
40 - CPLD reg offset: 0x21
44 - CPLD reg offset: 0x22
45 - Bits [3:0]
48 - CPLD reg offset: 0x22
56 - [0,0,0,0] = LED OFF
[all …]
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| /Documentation/devicetree/bindings/ipmi/ |
| D | ipmi-ipmb.yaml | 28 description: The address of the BMC on the IPMB bus. Defaults to 0x20.
57 #size-cells = <0>;
62 reg = <0x40>;
63 bmcaddr = /bits/ 8 <0x20>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm6345-l1-intc.txt | 47 reg = <0x10000020 0x20>,
48 <0x10000040 0x20>;
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| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx,can.yaml | 121 reg = <0xe0008000 0x1000>;
126 tx-fifo-depth = <0x40>;
127 rx-fifo-depth = <0x40>;
133 reg = <0x40000000 0x10000>;
134 clocks = <&clkc 0>, <&clkc 1>;
138 tx-fifo-depth = <0x40>;
139 rx-fifo-depth = <0x40>;
145 reg = <0x40000000 0x2000>;
146 clocks = <&clkc 0>, <&clkc 1>;
150 tx-mailbox-count = <0x20>;
[all …]
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| /Documentation/devicetree/bindings/serial/ |
| D | brcm,bcm7271-uart.yaml | 75 reg = <0x840d000 0x20>;
77 interrupts = <0x0 0x62 0x4>;
85 reg = <0x840e000 0x20>,
86 <0x840e080 0x8>,
87 <0x840e100 0xa8>,
88 <0x840e200 0x4c>,
89 <0x840e300 0x30>;
91 interrupts = <0x0 0x62 0x4>, <0x0 0x75 0x4>;
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl,sec-v4.0.yaml | 5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
42 - const: fsl,sec-v5.0
43 - const: fsl,sec-v4.0
47 - fsl,sec-v5.0
48 - const: fsl,sec-v4.0
49 - const: fsl,sec-v4.0
83 '^jr@[0-9a-f]+$':
98 - const: fsl,sec-v5.0-job-ring
99 - const: fsl,sec-v4.0-job-ring
101 - const: fsl,sec-v5.0-job-ring
[all …]
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mux.yaml | 30 const: 0
33 '^i2c@[0-9a-f]+$':
47 * An NXP pca9548 8 channel I2C multiplexer at address 0x70
53 #size-cells = <0>;
57 reg = <0x70>;
59 #size-cells = <0>;
63 #size-cells = <0>;
70 reg = <0x20>;
75 #size-cells = <0>;
82 reg = <0x20>;
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| /Documentation/hwmon/ |
| D | ltc3815.rst | 30 at address 0x20 on I2C bus #1::
33 # echo ltc3815 0x20 > /sys/bus/i2c/devices/i2c-1/new_device
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| /Documentation/devicetree/bindings/media/ |
| D | qcom,sc7280-venus.yaml | 102 reg = <0x0aa00000 0xd0600>;
118 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
119 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
122 iommus = <&apps_smmu 0x2180 0x20>,
123 <&apps_smmu 0x2184 0x20>;
136 iommus = <&apps_smmu 0x21a2 0x0>;
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| /Documentation/devicetree/bindings/timer/ |
| D | socionext,milbeaut-timer.txt | 14 reg = <0x1e000050 0x20>
15 interrupts = <0 91 4>;
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| D | marvell,orion-timer.txt | 12 reg = <0x20300 0x20>;
15 clocks = <&core_clk 0>;
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| /Documentation/devicetree/bindings/power/reset/ |
| D | axxia-reset.txt | 14 reg = <0x20 0x10030000 0 0x2000>;
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| /Documentation/devicetree/bindings/rtc/ |
| D | orion-rtc.txt | 16 reg = <0xd0010300 0x20>;
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | counter.txt | 13 reg = <0x4a304000 0x20>;
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