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/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
53 typically 0 as this is the start of the bank.
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
99 reg = <0x12560000 0x14>;
[all …]
/Documentation/devicetree/bindings/crypto/
Dfsl-sec6.txt23 Definition: Must include "fsl,sec-v6.0".
63 compatible = "fsl,sec-v6.0";
67 reg = <0xa0000 0x20000>;
68 ranges = <0 0xa0000 0x20000>;
84 Definition: Must include "fsl,sec-v6.0-job-ring".
103 compatible = "fsl,sec-v6.0-job-ring";
104 reg = <0x1000 0x1000>;
105 interrupts = <49 2 0 0>;
115 In qoriq-sec6.0.dtsi:
117 compatible = "fsl,sec-v6.0";
[all …]
Dmediatek-crypto.txt16 reg = <0 0x1b240000 0 0x20000>;
/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-qmss.txt27 external link ram entries. If the address is specified as "0"
83 0 : None, i.e interrupt on list full only
123 queue-range = <0 0x4000>;
124 linkram0 = <0x100000 0x8000>;
125 linkram1 = <0x0 0x10000>;
132 managed-queues = <0 0x2000>;
133 reg = <0x2a40000 0x20000>,
134 <0x2a06000 0x400>,
135 <0x2a02000 0x1000>,
136 <0x2a03000 0x1000>,
[all …]
/Documentation/devicetree/bindings/sram/
Dsram.yaml159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
163 ranges = <0 0x5c000000 0x40000>;
166 reg = <0x100 0x50>;
170 reg = <0x1000 0x1000>;
175 reg = <0x20000 0x20000>;
190 reg = <0x02020000 0x54000>;
193 ranges = <0 0x02020000 0x54000>;
195 smp-sram@0 {
197 reg = <0x0 0x1000>;
202 reg = <0x53000 0x1000>;
[all …]
/Documentation/devicetree/bindings/media/
Damphion,vpu.yaml20 pattern: "^vpu@[0-9a-f]+$"
43 "^mailbox@[0-9a-f]+$":
50 "^vpu-core@[0-9a-f]+$":
116 ranges = <0x2c000000 0x2c000000 0x2000000>;
117 reg = <0x2c000000 0x1000000>;
124 reg = <0x2d000000 0x20000>;
125 interrupts = <0 472 4>;
132 reg = <0x2d020000 0x20000>;
133 interrupts = <0 473 4>;
140 reg = <0x2d040000 0x20000>;
[all …]
Daspeed-video.txt27 reg = <0x1e700000 0x20000>;
/Documentation/devicetree/bindings/virtio/
Dpci-iommu.yaml40 BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be
63 reg = <0x0 0x40000000 0x0 0x1000000>;
64 ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;
70 iommu-map = <0x0 &iommu0 0x0 0x8
71 0x9 &iommu0 0x9 0xfff7>;
74 iommu0: iommu@1,0 {
76 reg = <0x800 0 0 0 0>;
85 reg = <0x0 0x50000000 0x0 0x1000000>;
86 ranges = <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0f000000>;
90 * with endpoint IDs 0x10000 - 0x1ffff
[all …]
/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/Documentation/devicetree/bindings/dma/ti/
Dk3-bcdma.yaml50 0 - split channel
56 if cell 1 is 0 (split channel):
59 for source thread IDs (rx): 0 - 0x7fff
60 for destination thread IDs (tx): 0x8000 - 0xffff
95 maximum: 0x3f
106 maximum: 0x3f
117 maximum: 0x3f
219 reg = <0x0 0x485c0100 0x0 0x100>,
220 <0x0 0x4c000000 0x0 0x20000>,
221 <0x0 0x4a820000 0x0 0x20000>,
[all …]
/Documentation/devicetree/bindings/clock/
Dlsi,axm5516-clks.txt18 reg = <0x20 0x10020000 0 0x20000>;
23 reg = <0x20 0x10080000 0 0x1000>;
Dqcom,sm6375-dispcc.yaml45 reg = <0x05f00000 0x20000>;
48 <&dsi_phy 0>,
Dqcom,sm6115-dispcc.yaml59 reg = <0x5f00000 0x20000>;
62 <&dsi0_phy 0>,
Dqcom,dispcc-sm6350.yaml69 reg = <0x0af00000 0x20000>;
72 <&dsi_phy 0>,
74 <&dp_phy 0>,
/Documentation/devicetree/bindings/interrupt-controller/
Dmti,gic.yaml61 - minimum: 0
112 reg = <0x1bdc0000 0x20000>;
130 reg = <0x1bdc0000 0x20000>;
Dti,pruss-intc.yaml18 interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
37 pattern: "^interrupt-controller@[0-9a-f]+$"
66 pattern: host_intr[0-7]
88 Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
114 pruss: pruss@0 {
116 reg = <0x0 0x80000>;
123 reg = <0x20000 0x2000>;
138 pruss@0 {
140 reg = <0x0 0x40000>;
147 reg = <0x20000 0x2000>;
[all …]
Darm,gic-v3.yaml33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
99 multipleOf: 0x10000
100 exclusiveMinimum: 0
[all …]
/Documentation/devicetree/bindings/reserved-memory/
Dqcom,cmd-db.yaml42 reg = <0x85fe0000 0x20000>;
/Documentation/devicetree/bindings/reset/
Dqcom,pdc-global.yaml49 reg = <0xb2e0000 0x20000>;
Dintel,rcu-gw.yaml28 minimum: 0
54 reg = <0xe0000000 0x20000>;
55 intel,global-reset = <0x10 30>;
61 reg = <0xe0d00000 0x30>;
64 resets = <&rcu0 0x30 21>;
/Documentation/devicetree/bindings/timer/
Dnxp,sysctr-timer.yaml54 reg = <0x306a0000 0x20000>;
Dti,davinci-timer.txt30 reg = <0x20000 0x1000>;
/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt12 "fsl,pamu-v1.0". The second is "fsl,pamu".
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
19 is 0x5000.
56 For PAMU v1.0, this size is 0x1000.
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
96 reg = <0x20000 0x5000>;
97 ranges = <0 0x20000 0x5000>;
98 fsl,portid-mapping = <0xf80000>;
102 24 2 0 0
105 pamu0: pamu@0 {
[all …]
/Documentation/devicetree/bindings/net/
Drenesas,r8a779f0-ether-switch.yaml99 const: 0
102 "^port@[0-9a-f]+$":
150 reg = <0xe6880000 0x20000>, <0xe68c0000 0x20000>;
230 #size-cells = <0>;
231 port@0 {
232 reg = <0>;
235 phys = <&eth_serdes 0>;
238 #size-cells = <0>;
248 #size-cells = <0>;
258 #size-cells = <0>;
/Documentation/devicetree/bindings/usb/
Dbrcm,usb-pinmap.yaml63 reg = <0x22000d0 0x4>;
64 in-gpios = <&gpio 18 0>, <&gpio 19 0>;
66 brcm,in-masks = <0x8000 0x40000 0x10000 0x80000>;
67 out-gpios = <&gpio 20 0>;
69 brcm,out-masks = <0x20000 0x800000 0x400000 0x200000>;
70 interrupts = <0x0 0xb2 0x4>;

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