Searched full:47 (Results 1 – 25 of 130) sorted by relevance
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| /Documentation/hwmon/ |
| D | smsc47m1.rst | 16 http://www.smsc.com/media/Downloads_Public/Data_Sheets/47b272.pdf
18 http://www.smsc.com/media/Downloads_Public/Data_Sheets/47m10x.pdf
20 http://www.smsc.com/media/Downloads_Public/Data_Sheets/47m112.pdf
56 The Standard Microsystems Corporation (SMSC) 47M1xx Super I/O chips
64 No documentation is available for the 47M997, but it has the same device
65 ID as the 47M15x and 47M192 chips and seems to be compatible.
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| D | f71805f.rst | 86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
87 in4 VIN4 VCC5V 200K 47K 5.25 0.95 V
91 in8 VIN8 VSB5V 200K 47K 1.00 0.95 V
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| /Documentation/translations/zh_CN/core-api/ |
| D | packing.rst | 61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
75 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
87 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
100 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
112 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
124 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
134 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
145 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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| /Documentation/arch/x86/x86_64/ |
| D | 5level-paging.rst | 43 above 47-bit by default.
46 specifying hint address (with or without MAP_FIXED) above 47-bits.
48 If hint address set above 47-bit, but MAP_FIXED is not specified, we try
51 from 47-bit window.
58 to allocation from 47-bit address space.
65 MPX (without MAWA extension) cannot handle addresses above 47-bit, so we
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| /Documentation/core-api/ |
| D | packing.rst | 55 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
71 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
84 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
98 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
110 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
125 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
136 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
147 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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| /Documentation/arch/arm64/ |
| D | kasan-offsets.sh | 15 print_kasan_offset 47 3
23 print_kasan_offset 47 4
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| D | memory.rst | 66 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
74 | +-------------------------------> [47:39] L0 index
81 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
88 | +-------------------------------> [47:42] L1 index (48-bit)
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | memory.txt | 87 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
95 | +-------------------------------> [47:39] L0 索引
102 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
109 | +-------------------------------> [47:42] L1 索引
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | memory.txt | 83 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
91 | +-------------------------------> [47:39] L0 索引
98 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
105 | +-------------------------------> [47:42] L1 索引
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| /Documentation/devicetree/bindings/rtc/ |
| D | nxp,lpc1788-rtc.txt | 18 interrupts = <47>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,ipq5018-tlmm.yaml | 38 maxItems: 47
108 gpio-ranges = <&tlmm 0 0 47>;
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| /Documentation/devicetree/bindings/media/ |
| D | hix5hd2-ir.txt | 23 interrupts = <0 47 4>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | nuvoton,npcm-wdt.txt | 27 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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| /Documentation/devicetree/bindings/display/armada/ |
| D | marvell,dove-lcd.txt | 27 interrupts = <47>;
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| /Documentation/devicetree/bindings/iio/light/ |
| D | st,uvis25.yaml | 35 uv-sensor@47 {
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| /Documentation/devicetree/bindings/serial/ |
| D | fsl,s32-linflexuart.yaml | 12 frames. See chapter 47 ("LINFlexD") in the reference manual
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| /Documentation/riscv/ |
| D | vm-layout.rst | 25 "must have bits 63–48 all equal to bit 47, or else a page-fault exception will
154 :code:`1 << 47` must be provided. Note that this is 47 due to sv48 userspace
155 ending at :code:`1 << 47` and the addresses beyond this are reserved for the
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| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr5.yaml | 24 Serial IDs read from Mode Registers 47 through 54. One byte per uint32
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| /Documentation/devicetree/bindings/timer/ |
| D | nxp,sysctr-timer.yaml | 57 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 226 power-domains = <&k3_pds 47>;
227 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-iommu | 26 filter_domain = "config1:32-47" - Domain ID filter
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| /Documentation/devicetree/bindings/sound/ |
| D | allwinner,sun8i-a33-codec.yaml | 64 clocks = <&ccu 47>, <&ccu 92>;
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| /Documentation/devicetree/bindings/clock/ |
| D | imx28-clock.yaml | 66 ssp1 47
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | chrontel,ch7322.yaml | 63 interrupts = <47 IRQ_TYPE_EDGE_RISING>;
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| /Documentation/devicetree/bindings/display/panel/ |
| D | sgd,gktw70sdae4se.yaml | 72 hsync-len = <47>;
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