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/Documentation/networking/
D6pack.rst4 6pack Protocol
7 This is the 6pack-mini-HOWTO, written by
17 1. What is 6pack, and what are the advantages to KISS?
20 6pack is a transmission protocol for data exchange between the PC and
23 6pack has two major advantages:
37 (however, this feature is not supported yet by the Linux 6pack driver).
44 More details about 6pack are described in the file 6pack.ps that is located
47 2. Who has developed the 6pack protocol?
50 The 6pack protocol has been developed by Ekki Plicht DF4OR, Henning Rech
51 DF9IC and Gunter Jost DK7WJ. A driver for 6pack, written by Gunter Jost and
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D6lowpan.rst4 Netdev private dataroom for 6lowpan interfaces
7 All 6lowpan able net devices, means all interfaces with ARPHRD_6LOWPAN,
14 Where LL_PRIV_6LOWPAN_DATA is sizeof linklayer 6lowpan private data struct.
25 wheres LOWPAN_LLTYPE_FOOBAR is a define for your 6LoWPAN linklayer type of
42 /* do 802.15.4 6LoWPAN handling here */
51 In case of generic 6lowpan branch ("net/6lowpan") you can remove the check
/Documentation/networking/device_drivers/can/ctu/
Dfsm_txt_buffer_user.svg5 …<path transform="scale(-.6)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
8 …<path transform="scale(-.6)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
11 …<path transform="scale(-.6)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
14 …<path transform="scale(-.6)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
17 …<path transform="scale(-.6)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
20 …<path transform="scale(-.6)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
23 … transform="scale(.6) rotate(180) translate(0)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.0177…
26 … transform="scale(.6) rotate(180) translate(0)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.0177…
29 … transform="scale(.6) rotate(180) translate(0)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.0177…
32 … transform="scale(.6) rotate(180) translate(0)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.0177…
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/Documentation/devicetree/bindings/pinctrl/
Dfsl,vf610-pinctrl.txt22 PAD_CTL_DSE_DISABLE (0 << 6)
23 PAD_CTL_DSE_150ohm (1 << 6)
24 PAD_CTL_DSE_75ohm (2 << 6)
25 PAD_CTL_DSE_50ohm (3 << 6)
26 PAD_CTL_DSE_37ohm (4 << 6)
27 PAD_CTL_DSE_30ohm (5 << 6)
28 PAD_CTL_DSE_25ohm (6 << 6)
29 PAD_CTL_DSE_20ohm (7 << 6)
Dfsl,imx6ul-pinctrl.txt8 "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
9 - fsl,pins: each entry consists of 6 integers and represents the mux and config
25 PAD_CTL_SPEED_LOW (0 << 6)
26 PAD_CTL_SPEED_MED (1 << 6)
27 PAD_CTL_SPEED_HIGH (3 << 6)
34 PAD_CTL_DSE_43ohm (6 << 3)
Dfsl,imx6sx-pinctrl.txt8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
24 PAD_CTL_SPEED_LOW (0 << 6)
25 PAD_CTL_SPEED_MED (1 << 6)
26 PAD_CTL_SPEED_HIGH (3 << 6)
33 PAD_CTL_DSE_43ohm (6 << 3)
Dfsl,imx6sll-pinctrl.txt8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
25 PAD_CTL_SPEED_LOW (0 << 6)
26 PAD_CTL_SPEED_MED (1 << 6)
27 PAD_CTL_SPEED_HIGH (3 << 6)
34 PAD_CTL_DSE_43ohm (6 << 3)
/Documentation/translations/zh_CN/core-api/
Dpacking.rst62 7 6 5 4
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
88 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
101 4 5 6 7
102 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
113 7 6 5 4
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/Documentation/input/devices/
Delantech.rst24 5.2 Native absolute mode 6 byte packet format
28 6. Hardware version 3
30 6.2 Native absolute mode 6 byte packet format
35 7.2 Native absolute mode 6 byte packet format
41 8.2 Native relative mode 6 byte packet format
52 packet. Version 2 seems to be introduced with the EeePC and uses 6 bytes
54 and width of the touch. Hardware version 3 uses 6 bytes per packet (and
55 for 2 fingers the concatenation of two 6 bytes packets) and allows tracking
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
61 separate packet format. It is also 6 bytes per packet.
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/Documentation/driver-api/media/drivers/
Dsh_mobile_ceu_camera.rst30 | `. .6--
32 | . .6'-
52 S_FMT(width / height = (6') - (6))
64 (6) to (6') - CEU scale - user window
84 scale_comb = width_u / ((6') - (6))
95 6. Retrieve sensor output window (g_fmt)
127 Cropping is performed in the following 6 steps:
132 to 2 : 2', target crop 5 : 5', current output format 6' - 6.
140 5. Calculate and apply host scale = (6' - 6) / (4' - 4)
142 6. Calculate and apply host crop: 6 - 7 = (5 - 2) * (6' - 6) / (5' - 5)
/Documentation/dev-tools/
Dkmemleak.rst245 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk
246 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5 kkkkkkkkkkkkkkk.
/Documentation/leds/
Dleds-blinkm.rst25 $ ls -h /sys/class/leds/blinkm-6-*
26 /sys/class/leds/blinkm-6-9-blue:
29 /sys/class/leds/blinkm-6-9-green:
32 /sys/class/leds/blinkm-6-9-red:
35 (same is /sys/bus/i2c/devices/6-0009/leds)
42 $ cat blinkm-6-9-blue/brightness
45 $ echo 200 > blinkm-6-9-blue/brightness
49 $ echo heartbeat > blinkm-6-9-green/trigger
58 E.g. below /sys/bus/i2c/devices/6-0009/blinkm
60 $ ls -h /sys/bus/i2c/devices/6-0009/blinkm/
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/Documentation/hwmon/
Dlt7182s.rst22 LT7182S is a Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher with
72 in[3-4|6-7]_label "vout[1-2]"
73 in[3-4|6-7]_input Measured output voltage
74 in[3-4|6-7]_highest Highest measured output voltage
75 in[3-4|6-7]_lcrit Critical minimum output voltage
76 in[3-4|6-7]_lcrit_alarm Output voltage critical low alarm
77 in[3-4|6-7]_min Minimum output voltage
78 in[3-4|6-7]_max_alarm Output voltage low alarm
79 in[3-4|6-7]_max Maximum output voltage
80 in[3-4|6-7]_max_alarm Output voltage high alarm
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Dmax34440.rst70 This driver supports hardware monitoring for Maxim MAX34440 PMBus 6-Channel
113 in[1-6]_label "vout[1-6]".
114 in[1-6]_input Measured voltage. From READ_VOUT register.
115 in[1-6]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
116 in[1-6]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
117 in[1-6]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
118 in[1-6]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
120 in[1-6]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
121 in[1-6]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
122 in[1-6]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
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Dmax31785.rst44 in[1-6]_crit Critical maximum output voltage
45 in[1-6]_crit_alarm Output voltage critical high alarm
46 in[1-6]_input Measured output voltage
47 in[1-6]_label "vout[18-23]"
48 in[1-6]_lcrit Critical minimum output voltage
49 in[1-6]_lcrit_alarm Output voltage critical low alarm
50 in[1-6]_max Maximum output voltage
51 in[1-6]_max_alarm Output voltage high alarm
52 in[1-6]_min Minimum output voltage
53 in[1-6]_min_alarm Output voltage low alarm
/Documentation/userspace-api/media/rc/
Drc-protos.rst55 - 6 (inverted)
57 - 2nd start bit in rc5, re-used as 6th command bit
71 * - 6
78 where there the second stop bit is the 6th command bit, but inverted.
80 schemes. This bit is stored in bit 6 of the scancode, inverted. This is
115 * - 6
117 - 6 to 11
121 * - 6
166 * - 6
172 * - 6
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/Documentation/userspace-api/media/v4l/
Dsubdev-formats.rst258 - 6
1003 - r\ :sub:`6`
1011 - b\ :sub:`6`
1019 - g\ :sub:`6`
1151 - b\ :sub:`6`
1159 - g\ :sub:`6`
1167 - r\ :sub:`6`
1204 - b\ :sub:`6`
1239 - g\ :sub:`6`
1274 - r\ :sub:`6`
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Dpixfmt-packed-hsv.rst46 - 6
55 - 6
64 - 6
73 - 6
95 - h\ :sub:`6`
104 - s\ :sub:`6`
113 - v\ :sub:`6`
126 - h\ :sub:`6`
135 - s\ :sub:`6`
144 - v\ :sub:`6`
/Documentation/core-api/
Dpacking.rst56 7 6 5 4
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
72 7 6 5 4
73 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
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86 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
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100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
108 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
111 7 6 5 4
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/Documentation/gpu/amdgpu/
Ddgpu-asic-info-table.csv2 AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, --
3 AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
4 AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
5 AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
6 AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE…
11 AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
Dapu-asic-info-table.csv2 Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3, n/a
9 Ryzen 7000 series (AM5), Raphael, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5
10 Ryzen 7x45 series (FL1), / Dragon Range, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5
11 Ryzen 7x20 series, Mendocino, 3.1.6, 10.3.7, 3.1.1, 5.2.7, 13.0.8
/Documentation/devicetree/bindings/crypto/
Dfsl-sec6.txt1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
4 -SEC 6 Node
9 SEC 6 Node
13 Node defines the base address of the SEC 6 block.
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
48 address and length of the SEC 6 configuration registers.
64 fsl,sec-era = <6>;
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/Documentation/devicetree/bindings/leds/
Dti,tca6507.yaml39 "^led@[0-6]$":
47 maximum: 6
52 "^gpio@[0-6]$":
61 maximum: 6
71 "^gpio@[0-6]$":
103 gpio-line-names = "wifi_reset@6";
128 gpio@6 {
/Documentation/devicetree/bindings/iio/amplifiers/
Dadi,hmc425a.yaml7 title: HMC425A 6-bit Digital Step Attenuator
14 HMC425A 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz
26 Must contain an array of 6 GPIO specifiers, referring to the GPIO pins
28 minItems: 6
29 maxItems: 6
/Documentation/gpu/amdgpu/display/
Dpipeline_4k_split.svg32 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
47 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
77 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
92 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
108 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
121 id="path1200-9-6"
123 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
136 id="path1200-9-6-9"
138 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
151 id="path1200-9-6-9-9"
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