Searched full:base (Results 1 – 25 of 1019) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-cgu.txt | 5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
25 Shall define the base and range of the address space
29 are the base clock numbers defined below.
35 Shall be an ordered list of numbers defining the base clock
41 Which base clocks that are available on the CGU depends on the
42 specific LPC part. Base clocks are numbered from 0 to 27.
45 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
46 1 BASE_USB0_CLK Base clock for USB0
47 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
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| D | nspire-clock.txt | 7 "lsi,nspire-cx-clock" for the base clock in the CX model
8 "lsi,nspire-classic-clock" for the base clock in the older model
10 - reg: Physical base address of the controller and length of memory mapped
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| /Documentation/devicetree/bindings/cache/ |
| D | qcom,llcc.yaml | 64 - description: LLCC0 base register region
65 - description: LLCC broadcast base register region
81 - description: LLCC0 base register region
82 - description: LLCC1 base register region
83 - description: LLCC broadcast base register region
101 - description: LLCC0 base register region
102 - description: LLCC1 base register region
103 - description: LLCC2 base register region
104 - description: LLCC3 base register region
105 - description: LLCC4 base register region
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| /Documentation/driver-api/ |
| D | infrastructure.rst | 20 Device Drivers Base
23 .. kernel-doc:: drivers/base/init.c
29 .. kernel-doc:: drivers/base/driver.c
32 .. kernel-doc:: drivers/base/core.c
35 .. kernel-doc:: drivers/base/syscore.c
41 .. kernel-doc:: drivers/base/class.c
44 .. kernel-doc:: drivers/base/node.c
47 .. kernel-doc:: drivers/base/transport_class.c
50 .. kernel-doc:: drivers/base/dd.c
56 .. kernel-doc:: drivers/base/platform.c
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| D | auxiliary_bus.rst | 9 .. kernel-doc:: drivers/base/auxiliary.c
15 .. kernel-doc:: drivers/base/auxiliary.c
25 .. kernel-doc:: drivers/base/auxiliary.c
42 .. kernel-doc:: drivers/base/auxiliary.c
48 .. kernel-doc:: drivers/base/auxiliary.c
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| /Documentation/i2c/busses/ |
| D | scx200_acb.rst | 12 * base: up to 4 ints
13 Base addresses for the ACCESS.bus controllers on SCx200 and SC1100 devices
15 By default the driver uses two base addresses 0x820 and 0x840.
16 If you want only one base address, specify the second as 0 so as to
28 The SC1100 WRAP boards are known to use base addresses 0x810 and 0x820.
32 scx200_acb.base=0x810,0x820
37 options scx200_acb base=0x810,0x820
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| /Documentation/arch/x86/x86_64/ |
| D | fsgs.rst | 12 The segment base address is added to the Byte-address to compute the
15 selection of a particular instance is purely based on the base-address in
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
32 variables. Each thread has its own FS base address so common code can be
41 Reading and writing the FS/GS base address
44 There exist two mechanisms to read and write the FS/GS base address:
50 Accessing FS/GS base with arch_prctl()
56 Reading the base:
61 Writing the base:
69 Accessing FS/GS base with the FSGSBASE instructions
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| /Documentation/admin-guide/device-mapper/ |
| D | snapshot.rst | 105 lvcreate -L 1G -n base volumeGroup
106 lvcreate -L 100M --snapshot -n snap volumeGroup/base
112 volumeGroup-base-real: 0 2097152 linear 8:19 384
115 volumeGroup-base: 0 2097152 snapshot-origin 254:11
118 brw------- 1 root root 254, 11 29 ago 18:15 /dev/mapper/volumeGroup-base-real
121 brw------- 1 root root 254, 10 29 ago 18:14 /dev/mapper/volumeGroup-base
142 volumeGroup-base-real: 0 2097152 linear 8:19 384
143 volumeGroup-base-cow: 0 204800 linear 8:19 2097536
144 volumeGroup-base: 0 2097152 snapshot-merge 254:11 254:12 P 16
147 brw------- 1 root root 254, 11 29 ago 18:15 /dev/mapper/volumeGroup-base-real
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
19 - SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
20 - SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1
161 # Phase-align the base time to the start of the next second.
169 base-time ${base_time} \
249 echo "base time ${base_time}"
252 action gate base-time ${base_time} \
262 echo "base time ${base_time}"
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| /Documentation/devicetree/bindings/phy/ |
| D | microchip,sparx5-serdes.yaml | 34 * 100 Mbps (100BASE-FX)
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
44 * 100 Mbps (100BASE-FX)
45 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
57 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
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| D | intel,keembay-phy-usb.yaml | 23 - const: cpr-apb-base
24 - const: slv-apb-base
42 reg-names = "cpr-apb-base", "slv-apb-base";
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| /Documentation/devicetree/bindings/net/ |
| D | ti,dp83869.yaml | 18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
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| D | hisilicon-hns-dsaf.txt | 13 - reg: specifies base physical address(es) and size of the device registers.
14 The first region is external interface control register base and size(optional,
17 The second region is SerDes base register and size(optional, only used when
20 The third region is the PPE register base and size.
21 The fourth region is dsa fabric base register and size. It is not required for
23 - reg-names: may be ppe-base and(or) dsaf-base. It is used to find the
64 reg-names = "ppe-base", "dsaf-base";
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| /Documentation/devicetree/bindings/nvmem/layouts/ |
| D | kontron,sl28-vpd.yaml | 14 number and a base MAC address. The actual MAC addresses for the
15 on-board ethernet devices are derived from this base MAC address by
30 base-mac-address:
33 Base MAC address for all on-module network interfaces. The first
58 base_mac_address: base-mac-address {
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| /Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 121 (icid-base,iommu,iommu-base,length).
123 Any ICID i in the interval [icid-base, icid-base + length) is
125 (i - icid-base + iommu-base).
131 (icid-base,gic-its,msi-base,length).
133 Any ICID in the interval [icid-base, icid-base + length) is
135 (i - icid-base + msi-base).
170 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | al,alpine-msix.txt | 8 - reg: physical base address and size of the registers
12 - al,msi-base-spi: SPI base of the MSI frame
23 al,msi-base-spi = <160>;
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| D | marvell,orion-intc.txt | 7 - reg: base address(es) of interrupt registers starting with CAUSE register
13 - 0 maps to bit 0 of first base address,
14 - 1 maps to bit 1 of first base address,
15 - 32 maps to bit 0 of second base address, and so on.
30 - reg: base address of bridge interrupt registers starting with CAUSE register
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| D | loongson,pch-pic.yaml | 24 loongson,pic-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
40 - loongson,pic-base-vec
54 loongson,pic-base-vec = <64>;
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| D | marvell,odmi-controller.txt | 23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
25 i.e marvell,spi-base = <128> will use SPI #96.
41 marvell,spi-base = <128>, <136>, <144>, <152>;
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| /Documentation/devicetree/bindings/sound/ |
| D | audio-graph-port.yaml | 15 port-base:
16 $ref: /schemas/graph.yaml#/$defs/port-base
27 endpoint-base:
28 $ref: /schemas/graph.yaml#/$defs/endpoint-base
105 $ref: "#/definitions/port-base"
109 $ref: "#/definitions/port-base"
113 $ref: "#/definitions/endpoint-base"
117 - $ref: "#/definitions/port-base"
121 $ref: "#/definitions/endpoint-base"
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| /Documentation/devicetree/bindings/arm/ |
| D | actions.yaml | 27 - caninos,labrador-base-m # Labrador Base Board M v1
32 - lemaker,guitar-bb-rev-b # LeMaker Guitar Base Board rev. B
39 - caninos,labrador-base-m2 # Labrador Base Board M v2
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| /Documentation/driver-api/media/drivers/ |
| D | radiotrack.rst | 56 The RadioTrack (base) ioport is configurable for 0x30c or 0x20c. Only one
129 Default: BASE <-- 0xc8 (current volume, no stereo detect,
132 Card Off: BASE <-- 0x00 (audio mute, no stereo detect,
135 Card On: BASE <-- 0x00 (see "Card Off", clears any unfinished business)
136 BASE <-- 0xc8 (see "Default")
138 Volume Down: BASE <-- 0x48 (volume down, no stereo detect,
141 BASE <-- 0xc8 (see "Default")
143 Volume Up: BASE <-- 0x88 (volume up, no stereo detect,
146 BASE <-- 0xc8 (see "Default")
148 Check Stereo: BASE <-- 0xd8 (current volume, stereo detect,
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| /Documentation/driver-api/firmware/ |
| D | request_firmware.rst | 20 .. kernel-doc:: drivers/base/firmware_loader/main.c
25 .. kernel-doc:: drivers/base/firmware_loader/main.c
30 .. kernel-doc:: drivers/base/firmware_loader/main.c
35 .. kernel-doc:: drivers/base/firmware_loader/main.c
40 .. kernel-doc:: drivers/base/firmware_loader/main.c
54 .. kernel-doc:: drivers/base/firmware_loader/main.c
68 .. kernel-doc:: drivers/base/firmware_loader/main.c
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| /Documentation/driver-api/surface_aggregator/clients/ |
| D | dtx.rst | 17 actions, such as unmounting devices attached to the base,
35 * **Base:**
40 The mechanism keeping the clipboard attached to the base in normal
59 *closed* state (default), the clipboard is secured to the base, whereas in
64 is intended to prevent the dGPU, positioned in the base of the device, from
77 on the base of the device or executing the ``SDTX_IOCTL_LATCH_REQUEST`` IOCTL.
94 can be detached from the base. This is the exact behavior as without
99 clipboard cannot be detached from the base. Furthermore, the EC sends
111 latch, after which the user can separate clipboard and base.
253 .. flat-table:: Base State Codes.
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
76 Intel(R) SST-BF (feature base-freq) is not supported
88 guaranteed base frequency. Once the user issues a command to use a specific
90 a change in the base frequency dynamically. This feature is called
112 base performance profile (which is performance level 0).
154 base-frequency(MHz):2600
156 speed-select-base-freq:disabled
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
185 speed-select-base-freq:unsupported
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