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/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt2 CPU topology binding description
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
32 The cpu nodes, as per bindings defined in [4], represent the devices that
35 A topology description containing phandles to cpu nodes that are not compliant
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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Dcpu-capacity.txt2 CPU capacity bindings
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
36 CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
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Didle-states.yaml4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
20 from simple wfi to power gating) according to OS PM policies. The CPU states
30 power states an ARM CPU can be put into are identified by the following list:
38 The power states described in the SBSA document define the basic CPU states on
74 The following diagram depicts the CPU execution phases and related timing
87 Diagram 1: CPU idle state execution phases
89 EXEC: Normal CPU execution.
94 (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
104 EXIT: Period during which the CPU is brought back to operational
114 CPU being able to execute normal code again. If not specified, this is assumed
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/Documentation/translations/zh_CN/driver-api/
Dio_ordering.rst28 CPU A: spin_lock_irqsave(&dev_lock, flags)
29 CPU A: val = readl(my_status);
30 CPU A: ...
31 CPU A: writel(newval, ring_ptr);
32 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
34 CPU B: spin_lock_irqsave(&dev_lock, flags)
35 CPU B: val = readl(my_status);
36 CPU B: ...
37 CPU B: writel(newval2, ring_ptr);
38 CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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/Documentation/ABI/testing/
Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/
5 A collection of both global and individual CPU attributes
7 Individual CPU attributes are contained in subdirectories
8 named by the kernel's logical CPU number, e.g.:
10 /sys/devices/system/cpu/cpuX/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
15 /sys/devices/system/cpu/possible
16 /sys/devices/system/cpu/present
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/Documentation/driver-api/
Dio_ordering.rst18 CPU A: spin_lock_irqsave(&dev_lock, flags)
19 CPU A: val = readl(my_status);
20 CPU A: ...
21 CPU A: writel(newval, ring_ptr);
22 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
24 CPU B: spin_lock_irqsave(&dev_lock, flags)
25 CPU B: val = readl(my_status);
26 CPU B: ...
27 CPU B: writel(newval2, ring_ptr);
28 CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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/Documentation/translations/zh_TW/
Dio_ordering.txt35 CPU A: spin_lock_irqsave(&dev_lock, flags)
36 CPU A: val = readl(my_status);
37 CPU A: ...
38 CPU A: writel(newval, ring_ptr);
39 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
41 CPU B: spin_lock_irqsave(&dev_lock, flags)
42 CPU B: val = readl(my_status);
43 CPU B: ...
44 CPU B: writel(newval2, ring_ptr);
45 CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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/Documentation/scheduler/
Dsched-bwc.rst6 This document only discusses CPU bandwidth control for SCHED_NORMAL.
10 specification of the maximum CPU bandwidth available to a group or hierarchy.
14 microseconds of CPU time. That quota is assigned to per-cpu run queues in
22 is transferred to cpu-local "silos" on a demand basis. The amount transferred
64 there many cgroups or CPU is under utilized, the interference is
70 Quota, period and burst are managed within the cpu subsystem via cgroupfs.
75 :ref:`Documentation/admin-guide/cgroup-v2.rst <cgroup-v2-cpu>`.
77 - cpu.cfs_quota_us: run-time replenished within a period (in microseconds)
78 - cpu.cfs_period_us: the length of a period (in microseconds)
79 - cpu.stat: exports throttling statistics [explained further below]
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Dsched-capacity.rst5 1. CPU Capacity
16 CPU capacity is a measure of the performance a CPU can reach, normalized against
17 the most performant CPU in the system. Heterogeneous systems are also called
18 asymmetric CPU capacity systems, as they contain CPUs of different capacities.
20 Disparity in maximum attainable performance (IOW in maximum CPU capacity) stems
32 CPU performance is usually expressed in Millions of Instructions Per Second
36 capacity(cpu) = work_per_hz(cpu) * max_freq(cpu)
41 Two different capacity values are used within the scheduler. A CPU's
43 attainable performance level. A CPU's ``capacity`` is its ``capacity_orig`` to
47 Note that a CPU's ``capacity`` is solely intended to be used by the CFS class,
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/Documentation/arch/x86/
Dtopology.rst84 A per-CPU variable containing:
114 CPU.
152 The alternative Linux CPU enumeration depends on how the BIOS enumerates the
154 That has the "advantage" that the logical Linux CPU numbers of threads 0 stay
160 [package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
166 [package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
167 -> [core 1] -> [thread 0] -> Linux CPU 1
171 [package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
172 -> [thread 1] -> Linux CPU 1
173 -> [core 1] -> [thread 0] -> Linux CPU 2
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/Documentation/devicetree/bindings/cpufreq/
Dbrcm,stb-avs-cpu-freq.txt4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5 references the mailbox register used to communicate with the AVS CPU[1]. The
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
15 [1] The AVS CPU is an independent co-processor that runs proprietary
22 Node brcm,avs-cpu-data-mem
26 - compatible: must include: brcm,avs-cpu-data-mem and
27 should include: one of brcm,bcm7271-avs-cpu-data-mem or
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/Documentation/devicetree/bindings/arm/
Dcpus.yaml14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
34 cpus and cpu node bindings definition
38 requires the cpus and cpu nodes to be present and contain the properties
55 bits [11:0] in CPU ID register.
60 required and matches the CPU MPIDR[23:0] register
220 - brcm,bcm11351-cpu-method
250 cpu-release-addr:
260 cpu-idle-states:
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Darm,coresight-cpu-debug.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
7 title: CoreSight CPU Debug Component
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
20 eventually the debug module connects with CPU for debugging. And the debug
22 CPU program counter, secure state and exception level, etc; usually every CPU
29 const: arm,coresight-cpu-debug
39 - const: arm,coresight-cpu-debug
51 cpu:
53 A phandle to the cpu this debug component is bound to.
60 dedicated power domain. CPU idle states may also need to be separately
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/Documentation/core-api/
Dcpu_hotplug.rst2 CPU hotplug in the Kernel
19 insertion and removal require support for CPU hotplug.
22 provisioning reasons, or for RAS purposes to keep an offending CPU off
23 system execution path. Hence the need for CPU hotplug support in the
26 A more novel use of CPU-hotplug support is its use today in suspend resume
59 CPU maps
72 after a CPU is available for kernel scheduling and ready to receive
73 interrupts from devices. Its cleared when a CPU is brought down using
75 migrated to another target CPU.
85 You really don't need to manipulate any of the system CPU maps. They should
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Dthis_cpu_ops.rst8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
68 per cpu area. It is then possible to simply use the segment override
69 to relocate a per cpu relative address to the proper per cpu area for
70 the processor. So the relocation to the per cpu base is encoded in the
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/Documentation/admin-guide/
Dkernel-per-CPU-kthreads.rst2 Reducing OS jitter due to per-cpu kthreads
5 This document lists per-CPU kthreads in the Linux kernel and presents
6 options to control their OS jitter. Note that non-per-CPU kthreads are
7 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind
8 them to a "housekeeping" CPU dedicated to such work.
23 - /sys/devices/system/cpu/cpuN/online: Control CPU N's hotplug state,
26 - In order to locate kernel-generated OS jitter on CPU N:
46 that does not require per-CPU kthreads. This will prevent these
52 3. Rework the eHCA driver so that its per-CPU kthreads are
65 some other CPU.
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Dcputopology.rst2 How CPU topology info is exported via sysfs
5 CPU topology info is exported via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/. Please refer to the ABI file:
8 Documentation/ABI/stable/sysfs-devices-system-cpu.
18 #define topology_physical_package_id(cpu)
19 #define topology_die_id(cpu)
20 #define topology_cluster_id(cpu)
21 #define topology_core_id(cpu)
22 #define topology_book_id(cpu)
23 #define topology_drawer_id(cpu)
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/Documentation/translations/zh_CN/mm/
Dmmu_notifier.rst43 CPU-thread-0 {尝试写到addrA}
44 CPU-thread-1 {尝试写到addrB}
45 CPU-thread-2 {}
46 CPU-thread-3 {}
50 CPU-thread-0 {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
51 CPU-thread-1 {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
52 CPU-thread-2 {}
53 CPU-thread-3 {}
57 CPU-thread-0 {COW_step1: {更新页表以指向addrA的新页}}
58 CPU-thread-1 {COW_step1: {更新页表以指向addrB的新页}}
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/Documentation/translations/zh_CN/scheduler/
Dsched-bwc.rst69 :ref:`Documentation/admin-guide/cgroup-v2.rst <cgroup-v2-cpu>`.
71 - cpu.cfs_quota_us：在一个时期内补充的运行时间（微秒）。
72 - cpu.cfs_period_us：一个周期的长度（微秒）。
73 - cpu.stat: 输出节流统计数据[下面进一步解释]
74 - cpu.cfs_burst_us：最大累积运行时间（微秒）。
78 cpu.cfs_period_us=100ms
79 cpu.cfs_quota_us=-1
80 cpu.cfs_burst_us=0
82 cpu.cfs_quota_us的值为-1表示该组没有任何带宽限制，这样的组被描述为无限制的带宽组。这代表
91 cpu.cfs_burst_us的值为0表示该组不能积累任何未使用的带宽。它使得CFS的传统带宽控制行为没有
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/Documentation/ABI/stable/
Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/dscr_default
6 /sys/devices/system/cpu/cpuN/dscr on all CPUs.
9 all per-CPU defaults at the same time.
12 What: /sys/devices/system/cpu/cpu[0-9]+/dscr
17 a CPU.
22 on any CPU where it executes (overriding the value described
27 What: /sys/devices/system/cpu/cpuX/topology/physical_package_id
33 What: /sys/devices/system/cpu/cpuX/topology/die_id
34 Description: the CPU die ID of cpuX. Typically it is the hardware platform's
39 What: /sys/devices/system/cpu/cpuX/topology/core_id
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/Documentation/power/
Dsuspend-and-cpuhotplug.rst2 Interaction of Suspend code (S3) with the CPU hotplug infrastructure
8 I. Differences between CPU hotplug and Suspend-to-RAM
11 How does the regular CPU hotplug code differ from how the Suspend-to-RAM
17 interactions involving the freezer and CPU hotplug and also tries to explain
21 What happens when regular CPU hotplug and Suspend-to-RAM race with each other
66 Common | before taking down the CPU |
79 Disable regular cpu hotplug
99 | Decrease cpu_hotplug_disabled, thereby enabling regular cpu hotplug
117 Regular CPU hotplug call path
121 /sys/devices/system/cpu/cpu*/online
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/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
20 * Alpine CPU resume registers
22 The CPU resume register are used to define required resume address after
26 - compatible : Should contain "al,alpine-cpu-resume".
32 The System-Fabric Service Registers allow various operation on CPU and
47 cpu@0 {
49 device_type = "cpu";
53 cpu@1 {
55 device_type = "cpu";
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/Documentation/mm/
Dmmu_notifier.rst8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
9 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
39 CPU-thread-0 {try to write to addrA}
40 CPU-thread-1 {try to write to addrB}
41 CPU-thread-2 {}
42 CPU-thread-3 {}
46 CPU-thread-0 {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
47 CPU-thread-1 {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
48 CPU-thread-2 {}
49 CPU-thread-3 {}
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/Documentation/RCU/
Dstallwarn.rst4 Using RCU's CPU Stall Detector
7 This document first discusses what sorts of issues RCU's CPU stall
13 What Causes RCU CPU Stall Warnings?
16 So your kernel printed an RCU CPU stall warning. The next question is
17 "What caused it?" The following problems can result in RCU CPU stall
20 - A CPU looping in an RCU read-side critical section.
22 - A CPU looping with interrupts disabled.
24 - A CPU looping with preemption disabled.
26 - A CPU looping with bottom halves disabled.
28 - For !CONFIG_PREEMPTION kernels, a CPU looping anywhere in the
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/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
24 will dump related registers for every CPU; finally this is good for assistant
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
61 state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
62 in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
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