Searched +full:cortex +full:- +full:a9 (Results 1 – 25 of 32) sorted by relevance
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
29 - arm,cortex-a5-scu
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| D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
22 - description: ARM RealView Emulation Baseboard (HBI-0140) was created
26 - const: arm,realview-eb
27 - description: ARM RealView Platform Baseboard for ARM1176JZF-S
28 (HBI-0147) was created as a development board to test ARM TrustZone,
31 - const: arm,realview-pb1176
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| D | calxeda.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
12 Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
13 or Cortex-A15 based ECX-2000 SOCs
20 - enum:
21 - calxeda,highbank
22 - calxeda,ecx-2000
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| D | actions.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
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| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,global_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
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| D | arm,twd-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
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| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | nuvoton,npcm750-smp | 2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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| D | marvell,berlin-smp | 2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-dt.txt | 11 - None
14 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
17 - clock-latency: Specify the possible maximum transition latency for clock,
19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
20 - #cooling-cells:
22 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
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| D | cpufreq-spear.txt | 2 -------------------
9 - cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the
13 - clock-latency: Specify the possible maximum transition latency for clock, in
20 --------
26 compatible = "arm,cortex-a9";
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| D | nvidia,tegra20-cpufreq.txt | 5 - clocks: Must contain an entry for the CPU clock.
6 See ../clocks/clock-bindings.txt for details.
7 - operating-points-v2: See ../bindings/opp/opp-v2.yaml for details.
8 - #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
10 For each opp entry in 'operating-points-v2' table:
11 - opp-supported-hw: Two bitfields indicating:
23 - opp-microvolt: CPU voltage triplet.
26 - cpu-supply: Phandle to the CPU power supply.
31 regulator-name = "vdd_cpu";
36 compatible = "operating-points-v2";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | arm,twd-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
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| /Documentation/devicetree/bindings/arm/ux500/ |
| D | boards.txt | 1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
20 compatible = "ste,dbx500-backupram"
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
29 see binding for timer/arm,twd-timer.yaml
36 /dts-v1/;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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| D | marvell,armada-370-xp-mpic.txt | 2 -----------------------------------------------------
5 - compatible: Should be "marvell,mpic"
6 - interrupt-controller: Identifies the node as an interrupt controller.
7 - msi-controller: Identifies the node as an PCI Message Signaled
9 - #interrupt-cells: The number of cells to define the interrupts. Should be 1.
12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
21 - interrupts: If defined, then it indicates that this MPIC is
24 connected as a slave to the Cortex-A9 GIC. The provided interrupt
29 mpic: interrupt-controller@d0020000 {
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,bcm63138.txt | 1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
24 - enable-method: should be "brcm,bcm63138"
25 - resets: phandle to the relevant PMB controller, one integer indicating the internal
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| D | brcm,hr2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 are based on Broadcom's iProc SoC architecture and feature a single core Cortex
12 A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
16 - Florian Fainelli <f.fainelli@gmail.com>
23 - enum:
24 - ubnt,unifi-switch8
25 - const: brcm,bcm53342
26 - const: brcm,hr2
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| D | brcm,nsp.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
14 DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
18 - Ray Jui <rjui@broadcom.com>
19 - Scott Branden <sbranden@broadcom.com>
26 - description: BCM58522 based boards
28 - enum:
29 - brcm,bcm958522er
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| /Documentation/arch/arm/sti/ |
| D | stih407-overview.rst | 6 ------------
8 The STiH407 is the new generation of SoC for Multi-HD, AVC set-top boxes
10 and IP-STB markets.
13 - ARM Cortex-A9 1.5 GHz dual core CPU (28nm)
14 - SATA2, USB 3.0, PCIe, Gbit Ethernet
17 ---------------
|
| D | stih418-overview.rst | 6 ------------
8 The STiH418 is the new generation of SoC for UHDp60 set-top boxes
10 and IP-STB markets.
13 - ARM Cortex-A9 1.5 GHz quad core CPU (28nm)
14 - SATA2, USB 3.0, PCIe, Gbit Ethernet
15 - HEVC L5.1 Main 10
16 - VP9
19 ---------------
|
| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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| D | opp-v1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
19 This binding only supports voltage-frequency pairs.
24 operating-points:
25 $ref: /schemas/types.yaml#/definitions/uint32-matrix
28 - description: Frequency in kHz
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| /Documentation/devicetree/bindings/nvmem/ |
| D | brcm,nvram.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 NVRAM can be accessed on Broadcom BCM47xx MIPS and Northstar ARM Cortex-A9
20 - Rafał Miłecki <rafal@milecki.pl>
23 - $ref: nvmem.yaml#
40 "#nvmem-cell-cells":
49 "#nvmem-cell-cells":
58 "#nvmem-cell-cells":
66 - |
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| /Documentation/arch/arm/ |
| D | marvell.rst | 13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
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