| /Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,dw-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
7 title: Renesas R-Car DWC HDMI TX Encoder
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: synopsys,dw-hdmi.yaml#
23 - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
24 - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
25 - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
26 - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
27 - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
28 - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
[all …]
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| D | ingenic,jz4780-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/bridge/ingenic,jz4780-hdmi.yaml#
7 title: Ingenic JZ4780 HDMI Transmitter
13 The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
17 - $ref: synopsys,dw-hdmi.yaml#
21 const: ingenic,jz4780-dw-hdmi
39 description: Link to the HDMI connector.
54 hdmi: hdmi@10180000 {
55 compatible = "ingenic,jz4780-dw-hdmi";
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| /Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,exynos-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
7 title: Samsung Exynos SoC HDMI
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
20 - samsung,exynos5420-hdmi
21 - samsung,exynos5433-hdmi
34 Phandle to the HDMI DDC node.
36 hdmi-en-supply:
38 Provides voltage source for DCC lines available on HDMI connector. When
40 HPD (hot plug detect) line, what causes HDMI block to stay turned off.
[all …]
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| /Documentation/devicetree/bindings/sound/ |
| D | imx-audio-hdmi.yaml | 4 $id: http://devicetree.org/schemas/sound/imx-audio-hdmi.yaml#
7 title: NXP i.MX audio complex with HDMI
15 - fsl,imx-audio-hdmi
26 hdmi-out:
30 of HDMI will be enabled, indicating there's a physical HDMI out
32 block, such as an HDMI encoder or display-controller.
34 hdmi-in:
38 HDMI will be enabled, indicating there is a physical HDMI in
50 sound-hdmi {
51 compatible = "fsl,imx-audio-hdmi";
[all …]
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| D | rockchip-max98090.txt | 13 - rockchip,hdmi-codec: The phandle of HDMI device for HDMI codec.
26 /* For HDMI-only board. */
31 rockchip,hdmi-codec = <&hdmi>;
34 /* For max98090 plus HDMI board. */
41 rockchip,hdmi-codec = <&hdmi>;
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| /Documentation/devicetree/bindings/display/ |
| D | amlogic,meson-dw-hdmi.yaml | 5 $id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
18 - A Synopsys DesignWare HDMI Controller IP
20 - A custom HDMI PHY in order to convert video to TMDS signal
22 | HDMI TOP |<= HPD
25 | Synopsys HDMI | HDMI PHY |=> TMDS
29 The HDMI TOP block only supports HPD sensing.
30 The Synopsys HDMI Controller interrupt is routed through the
32 Communication to the TOP Block and the Synopsys HDMI Controller is done
34 The HDMI PHY is configured by registers in the HHI register block.
[all …]
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| D | allwinner,sun4i-a10-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
7 title: Allwinner A10 HDMI Controller
10 The HDMI Encoder supports the HDMI video and audio outputs, and does
20 - const: allwinner,sun4i-a10-hdmi
21 - const: allwinner,sun5i-a10s-hdmi
22 - const: allwinner,sun6i-a31-hdmi
24 - const: allwinner,sun7i-a20-hdmi
25 - const: allwinner,sun5i-a10s-hdmi
36 - description: The HDMI interface clock
37 - description: The HDMI module clock
[all …]
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| D | brcm,bcm2835-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-hdmi.yaml#
7 title: Broadcom VC4 (VideoCore4) HDMI Controller
14 const: brcm,bcm2835-hdmi
18 - description: HDMI register range
27 - description: The HDMI state machine clock
32 - const: hdmi
42 The GPIO pin for the HDMI hotplug detect (if it doesn't appear
43 as an interrupt/status bit in the HDMI controller itself)
71 hdmi: hdmi@7e902000 {
72 compatible = "brcm,bcm2835-hdmi";
[all …]
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| D | brcm,bcm2711-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
7 title: Broadcom BCM2711 HDMI Controller
20 - description: HDMI controller register range
22 - description: HDMI PHY register range
32 - const: hdmi
44 - description: The HDMI state machine clock
46 - description: The HDMI Audio parent clock
47 - description: The HDMI CEC parent clock
51 - const: hdmi
82 The GPIO pin for the HDMI hotplug detect (if it doesn't appear
[all …]
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| D | allwinner,sun8i-a83t-hdmi-phy.yaml | 4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
7 title: Allwinner A83t HDMI PHY
19 - allwinner,sun8i-a83t-hdmi-phy
20 - allwinner,sun8i-h3-hdmi-phy
21 - allwinner,sun8i-r40-hdmi-phy
22 - allwinner,sun50i-a64-hdmi-phy
23 - allwinner,sun50i-h6-hdmi-phy
63 - allwinner,sun8i-r40-hdmi-phy
79 - allwinner,sun8i-h3-hdmi-phy
80 - allwinner,sun50i-a64-hdmi-phy
[all …]
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| D | allwinner,sun8i-a83t-dw-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
28 - const: allwinner,sun8i-a83t-dw-hdmi
29 - const: allwinner,sun50i-h6-dw-hdmi
33 - allwinner,sun8i-h3-dw-hdmi
34 - allwinner,sun8i-r40-dw-hdmi
35 - allwinner,sun50i-a64-dw-hdmi
[all …]
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| /Documentation/devicetree/bindings/display/msm/ |
| D | hdmi.yaml | 5 $id: http://devicetree.org/schemas/display/msm/hdmi.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI output
16 - qcom,hdmi-tx-8084
17 - qcom,hdmi-tx-8660
18 - qcom,hdmi-tx-8960
19 - qcom,hdmi-tx-8974
20 - qcom,hdmi-tx-8994
21 - qcom,hdmi-tx-8996
51 - hdmi-phy
57 hdmi-mux-supply:
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | amlogic,meson8-hdmi-tx-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#
7 title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY
13 The HDMI TX PHY node should be the child of a syscon node with the
23 pattern: "^hdmi-phy@[0-9a-f]+$"
29 - amlogic,meson8b-hdmi-tx-phy
30 - amlogic,meson8m2-hdmi-tx-phy
31 - const: amlogic,meson8-hdmi-tx-phy
32 - const: amlogic,meson8-hdmi-tx-phy
40 HDMI TMDS clock
53 hdmi-phy@3a0 {
[all …]
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| D | phy-rockchip-inno-hdmi.txt | 1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
18 Optional properties for rk3328-hdmi-phy:
24 hdmi_phy: hdmi-phy@12030000 {
25 compatible = "rockchip,rk3228-hdmi-phy";
37 hdmi: hdmi@200a0000 {
38 compatible = "rockchip,rk3228-dw-hdmi";
41 phy-names = "hdmi";
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| D | mediatek,hdmi-phy.yaml | 5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
21 pattern: "^hdmi-phy@[0-9a-f]+$"
27 - mediatek,mt7623-hdmi-phy
28 - const: mediatek,mt2701-hdmi-phy
29 - const: mediatek,mt2701-hdmi-phy
30 - const: mediatek,mt8173-hdmi-phy
31 - const: mediatek,mt8195-hdmi-phy
[all …]
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| D | qcom,hdmi-phy-other.yaml | 5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI phy
16 - qcom,hdmi-phy-8660
17 - qcom,hdmi-phy-8960
18 - qcom,hdmi-phy-8974
19 - qcom,hdmi-phy-8084
58 - qcom,hdmi-phy-8660
73 - qcom,hdmi-phy-8960
91 - qcom,hdmi-phy-8084
92 - qcom,hdmi-phy-8974
[all …]
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| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
7 title: NVIDIA Tegra HDMI Output Encoder
15 pattern: "^hdmi@[0-9a-f]+$"
20 - nvidia,tegra20-hdmi
21 - nvidia,tegra30-hdmi
22 - nvidia,tegra114-hdmi
23 - nvidia,tegra124-hdmi
26 - const: nvidia,tegra132-hdmi
27 - const: nvidia,tegra124-hdmi
42 - const: hdmi
[all …]
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| /Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip,dw-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
7 title: Rockchip DWC HDMI TX Encoder
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
24 - rockchip,rk3328-dw-hdmi
25 - rockchip,rk3399-dw-hdmi
26 - rockchip,rk3568-dw-hdmi
49 - description: The HDMI CEC controller main clock
[all …]
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| D | inno_hdmi-rockchip.txt | 1 Rockchip specific extensions to the Innosilicon HDMI
6 "rockchip,rk3036-inno-hdmi";
10 Phandle to hdmi controller clock, name should be "pclk"
12 HDMI interrupt number
17 Switch the iomux of HPD/CEC pins to HDMI function.
20 hdmi: hdmi@20034000 {
21 compatible = "rockchip,rk3036-inno-hdmi";
40 hdmi {
41 hdmi_ctl: hdmi-ctl {
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| /Documentation/devicetree/bindings/display/imx/ |
| D | fsl,imx6-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
7 title: Freescale i.MX6 DWC HDMI TX Encoder
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - fsl,imx6dl-hdmi
23 - fsl,imx6q-hdmi
37 The HDMI DDC bus can be connected to either a system I2C master or the
38 functionally-reduced I2C master contained in the DWC HDMI. When connected
45 phandle to the iomuxc-gpr region containing the HDMI multiplexer control
52 HDMI multiplexer. Each port shall have a single endpoint.
[all …]
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
7 title: Mediatek HDMI Encoder
14 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
20 - mediatek,mt2701-hdmi
21 - mediatek,mt7623-hdmi
22 - mediatek,mt8167-hdmi
23 - mediatek,mt8173-hdmi
34 - description: HDMI PLL
50 - const: hdmi
52 mediatek,syscon-hdmi:
[all …]
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| D | mediatek,hdmi-ddc.yaml | 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
7 title: Mediatek HDMI DDC
14 The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
19 - mediatek,mt7623-hdmi-ddc
20 - mediatek,mt8167-hdmi-ddc
21 - mediatek,mt8173-hdmi-ddc
51 compatible = "mediatek,mt8173-hdmi-ddc";
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| /Documentation/devicetree/bindings/display/connector/ |
| D | hdmi-connector.yaml | 4 $id: http://devicetree.org/schemas/display/connector/hdmi-connector.yaml#
7 title: HDMI Connector
14 const: hdmi-connector
17 description: The HDMI connector type
39 hdmi-pwr-supply:
40 description: Power supply for the HDMI +5V Power pin
44 description: Connection to controller providing HDMI signals
56 compatible = "hdmi-connector";
57 label = "hdmi";
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | adv7604.yaml | 7 title: Analog Devices ADV7604/10/11/12 video decoder with HDMI receiver
14 an integrated HDMI receiver. The ADV7604 has four multiplexed HDMI inputs
15 and one analog input, and the ADV7610/11 have one HDMI input and no analog
16 input. The ADV7612 is similar to the ADV7610/11 but has 2 HDMI inputs.
36 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
37 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
38 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
39 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
40 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
41 - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
[all …]
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| /Documentation/userspace-api/media/cec/ |
| D | cec-intro.rst | 8 HDMI connectors provide a single pin for use by the Consumer Electronics
10 HDMI cable to communicate. The protocol for CEC version 1.4 is defined
11 in supplements 1 (CEC) and 2 (HEAC or HDMI Ethernet and Audio Return
12 Channel) of the HDMI 1.4a (:ref:`hdmi`) specification and the
14 HDMI 2.0 (:ref:`hdmi2`) specification.
24 In addition, CEC can be implemented in HDMI receivers, transmitters and
25 in USB devices that have an HDMI input and an HDMI output and that
|