Searched full:mx8qxp (Results 1 – 8 of 8) sorted by relevance
| /Documentation/devicetree/bindings/display/bridge/ |
| D | fsl,imx8qxp-pxl2dpi.yaml | 7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
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| D | fsl,imx8qxp-ldb.yaml | 19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
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| /Documentation/devicetree/bindings/bus/ |
| D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
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| /Documentation/devicetree/bindings/phy/ |
| D | mixel,mipi-dsi-phy.yaml | 17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
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| /Documentation/devicetree/bindings/media/ |
| D | nxp,imx8-jpeg.yaml | 7 title: i.MX8QXP/QM JPEG decoder/encoder
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| D | amphion,vpu.yaml | 53 separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
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| /Documentation/devicetree/bindings/clock/ |
| D | imx8qxp-lpcg.yaml | 7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
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| /Documentation/devicetree/bindings/arm/ |
| D | fsl.yaml | 1190 - description: i.MX8QXP based Boards
1193 - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
1194 - fsl,imx8qxp-mek # i.MX8QXP MEK Board
1204 - description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules
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