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/Documentation/hwmon/
Dmax16065.rst11 Addresses scanned: -
15 http://datasheets.maxim-ic.com/en/ds/MAX16065-MAX16066.pdf
21 Addresses scanned: -
25 http://datasheets.maxim-ic.com/en/ds/MAX16067.pdf
31 Addresses scanned: -
35 http://datasheets.maxim-ic.com/en/ds/MAX16068.pdf
41 Addresses scanned: -
45 http://datasheets.maxim-ic.com/en/ds/MAX16070-MAX16071.pdf
47 Author: Guenter Roeck <linux@roeck-us.net>
51 -----------
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Dtmp513.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Eric Tremblay <etremblay@distech-controls.com>
25 -----------
28 The TMP512 (dual-channel) and TMP513 (triple-channel) are system monitors
29 that include remote sensors, a local temperature sensor, and a high-side current
30 shunt monitor. These system monitors have the capability of measuring remote
31 temperatures, on-chip temperatures, and system voltage/power/current
35 -40 to + 125 degrees with a resolution of 0.0625 degree C.
44 **temp[1-4]_input**
46 **temp[1-4]_crit**
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Dadm1025.rst10 Addresses scanned: I2C 0x2c - 0x2e
18 Addresses scanned: I2C 0x2c - 0x2d
24 * Only two possible addresses (0x2c - 0x2d).
29 - Chen-Yuan Wu <gwu@esoft.com>,
30 - Jean Delvare <jdelvare@suse.de>
33 -----------
35 (This is from Analog Devices.) The ADM1025 is a complete system hardware
36 monitor for microprocessor-based systems, providing measurement and limit
37 comparison of various system parameters. Five voltage measurement inputs
39 the processor core voltage. The ADM1025 can monitor a sixth power-supply
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Dwm831x.rst1 Kernel driver wm831x-hwmon
11 - http://www.wolfsonmicro.com/products/WM8310
12 - http://www.wolfsonmicro.com/products/WM8311
13 - http://www.wolfsonmicro.com/products/WM8312
18 -----------
21 monitor a range of system operating parameters, including the voltages
22 of the major supplies within the system. Currently the driver provides
26 ------------------
32 ----------------------
34 Temperatures are sampled by a 12 bit ADC. Chip and battery temperatures
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Dadt7462.rst17 -----------
19 This driver implements support for the Analog Devices ADT7462 chip family.
21 This chip is a bit of a beast. It has 8 counters for measuring fan speed. It
23 two. See the chip documentation for more details about the exact set of
24 configurations. This driver does not allow one to configure the chip; that is
25 left to the system designer.
27 A sophisticated control system for the PWM outputs is designed into the ADT7462
28 that allows fan speed to be adjusted automatically based on any of the three
43 ----------------
45 The ADT7462 have a 10-bit ADC and can therefore measure temperatures
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/Documentation/driver-api/
Dedac.rst5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
18 The individual DRAM chips on a memory stick. These devices commonly
32 A physical connector on the motherboard that accepts a single memory
33 stick. Also called as "slot" on several datasheets.
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
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Dsm501.rst9 The Silicon Motion SM501 multimedia companion chip is a multifunction device
15 ----
23 chips via the platform device and driver system.
25 On detection of a device, the core initialises the chip (which may
29 The core re-uses the platform device system as the platform device
30 system provides enough features to support the drivers without the
31 need to create a new bus-type and the associated code to go with it.
35 ---------
43 as this is by-far the most resource-sensitive of the on-chip functions.
59 -------------
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/Documentation/devicetree/bindings/watchdog/
Daspeed-wdt.txt4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
9 - reg: physical base address of the controller and length of memory mapped
14 - aspeed,reset-type = "cpu|soc|system|none"
16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
20 This is useful in situations where another watchdog engine on chip is
23 If 'aspeed,reset-type=' is not specified the default is to enable system
28 - cpu: Reset CPU on watchdog timeout
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/Documentation/devicetree/bindings/powerpc/fsl/
Dpmc.txt4 - compatible: "fsl,<chip>-pmc".
6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip
8 whose PMC is compatible, and implies deep-sleep capability.
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip
12 whose PMC is compatible, and implies deep-sleep capability.
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also
16 apply to "fsl,mpc8641d-pmc".
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/Documentation/devicetree/bindings/powerpc/4xx/
Dreboot.txt1 Reboot property to control system reboot on PPC4xx systems:
7 1 - PPC4xx core reset
8 2 - PPC4xx chip reset
9 3 - PPC4xx system reset (default)
17 reset-type = <2>; /* Use chip-reset */
/Documentation/devicetree/bindings/arm/
Datmel-sysregs.txt1 Atmel system registers
4 - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
5 - reg : Should contain registers location and length
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
11 shared across all System Controller members.
14 - compatible: Should be "microchip,sam9x60-pit64b"
15 - reg: Should contain registers location and length
16 - interrupts: Should contain interrupt for PIT64B timer
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Dsyna.txt3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
19 ---------------------------------------------------------------
30 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
32 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
38 model = "Sony NSZ-GS7";
39 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
46 CPU control register allows various operations on CPUs, like resetting them
50 - compatible: should be "marvell,berlin-cpu-ctrl"
51 - reg: address and length of the register set
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/Documentation/ABI/testing/
Dsysfs-bus-event_source-devices-hv_24x73 Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
4 Description: Read-only. Attribute group to describe the magic bits
6 (See ABI/testing/sysfs-bus-event_source-devices-format).
12 chip = "config:16-31"
13 core = "config:16-31"
14 domain = "config:0-3"
15 lpar = "config:0-15"
16 offset = "config:32-63"
17 vcpu = "config:16-31"
21 PM_PB_CYC = "domain=1,offset=0x80,chip=?,lpar=0x0"
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/Documentation/scsi/
D53c700.rst1 .. SPDX-License-Identifier: GPL-2.0
10 This driver supports the 53c700 and 53c700-66 chips. It also supports
12 does sync (-66 and 710 only), disconnects and tag command queueing.
29 define if the chipset must be supported in little endian mode on a big
30 endian architecture (used for the 700 on parisc).
33 Using the Chip Core Driver
36 In order to plumb the 53c700 chip core driver into a working SCSI
37 driver, you need to know three things about the way the chip is wired
38 into your system (or expansion card).
45 the SCSI Id from the card bios or whether the chip is wired for
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/Documentation/devicetree/bindings/bus/
Dsocionext,uniphier-system-bus.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier System Bus
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
12 some control signals. It supports up to 8 banks (chip selects).
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
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/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
11 CK, etc.) that connect one or more LPDDR chips to a host system. The main
12 purpose of this node is to overall LPDDR topology of the system, including the
13 amount of individual LPDDR chips and the ranks per chip.
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
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/Documentation/devicetree/bindings/net/
Dmarvell-bt-8xxx.txt2 ------
3 The 8997 devices supports multiple interfaces. When used on SDIO interfaces,
4 the btmrvl driver is used and when used on USB interface, the btusb driver is
9 - compatible : should be one of the following:
10 * "marvell,sd8897-bt" (for SDIO)
11 * "marvell,sd8997-bt" (for SDIO)
16 - marvell,cal-data: Calibration data downloaded to the device during
20 - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip.
21 firmware will use the pin to wakeup host system (u16).
22 - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host
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/Documentation/devicetree/bindings/devfreq/event/
Dsamsung,exynos-nocp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos NoC (Network on Chip) Probe
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
16 that the Network on Chip (NoC) probes detects are transported over the
18 packets with header or data on the data request response network, or as
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/Documentation/networking/device_drivers/atm/
Diphase.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ATM (i)Chip IA Linux Driver Source
9 --------------------------------------------------------------------------------
13 --------------------------------------------------------------------------------
18 This is the README file for the Interphase PCI ATM (i)Chip IA Linux driver
23 - A single VPI (VPI value of 0) is supported.
24 - Supports 4K VCs for the server board (with 512K control memory) and 1K
26 - UBR, ABR and CBR service categories are supported.
27 - Only AAL5 is supported.
28 - Supports setting of PCR on the VCs.
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/Documentation/driver-api/gpio/
Ddrivers-on-gpio.rst6 the right in-kernel and userspace APIs/ABIs for the job, and that these
10 - leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
13 - ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
14 i.e. a LED will turn on/off in response to a GPIO line going high or low
15 (and that LED may in turn use the leds-gpio as per above).
17 - gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
20 - gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
24 - gpio_mouse: drivers/input/mouse/gpio_mouse.c is used to provide a mouse with
29 - gpio-beeper: drivers/input/misc/gpio-beeper.c is used to provide a beep from
32 - extcon-gpio: drivers/extcon/extcon-gpio.c is used when you need to read an
[all …]
Dusing-gpio.rst12 Documentation/driver-api/gpio/drivers-on-gpio.rst
14 For any kind of mass produced system you want to support, such as servers,
18 help to refine it, see Documentation/process/submitting-patches.rst.
22 The userspace ABI is intended for one-off deployments. Examples are prototypes,
24 industrial automation, PLC-type use cases, door controllers, in short a piece
27 software-hardware interface to be set up. They should not have a natural fit
28 to any existing kernel subsystem and not be a good fit for an operating system,
41 The userspace ABI is a character device for each GPIO hardware unit (GPIO chip).
42 These devices will appear on the system as ``/dev/gpiochip0`` thru
48 and arbitration for multiple simultaneous consumers on the same GPIO chip.
/Documentation/devicetree/bindings/rtc/
Disil,isl12057.txt1 Intersil ISL12057 I2C RTC/Alarm chip
8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
38 that the pinctrl-related properties below are given for completeness and
39 may not be required or may be different depending on your system or
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/Documentation/devicetree/bindings/hwmon/
Dibm,occ-hwmon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/hwmon/ibm,occ-hwmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: IBM On-Chip Controller (OCC) accessed from a service processor
10 - Eddie James <eajames@linux.ibm.com>
13 The POWER processor On-Chip Controller (OCC) helps manage power and
14 thermals for the system. A service processor or baseboard management
21 - ibm,p9-occ-hwmon
22 - ibm,p10-occ-hwmon
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/Documentation/sound/soc/
Doverview.rst5 The overall project goal of the ALSA System on Chip (ASoC) layer is to
6 provide better ALSA support for embedded system-on-chip processors (e.g.
9 had some limitations:-
12 CPU. This is not ideal and leads to code duplication - for example,
17 event). These are quite common events on portable devices and often require
18 machine specific code to re-route audio, enable amps, etc., after such an
23 power on portable devices. There was also no support for saving
31 features :-
33 * Codec independence. Allows reuse of codec drivers on other platforms
43 internal power blocks depending on the internal codec audio routing and any
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/Documentation/devicetree/bindings/mfd/
Dtwl4030-power.txt5 binding only supports the complete shutdown of the system after poweroff.
8 - compatible : must be one of the following
9 "ti,twl4030-power"
10 "ti,twl4030-power-reset"
11 "ti,twl4030-power-idle"
12 "ti,twl4030-power-idle-osc-off"
14 The use of ti,twl4030-power-reset is recommended at least on
17 When using ti,twl4030-power-idle, the TI recommended configuration
20 When using ti,twl4030-power-idle-osc-off, the TI recommended
22 down during off-idle. Note that this does not work on all boards
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