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/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra-pinmux-common.yaml39 or groups. See the Tegra TRM and various pinmux spreadsheets for complete
54 Tegra TRM to determine which are valid for each pin or group.
87 values depends on the pingroup. See "CAL_DRVDN" in the Tegra TRM.
92 values depends on the pingroup. See "CAL_DRVUP" in the Tegra TRM.
107 power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the Tegra TRM.
169 valid values depends on the pingroup. See "DRVDN_SLWR" in the Tegra TRM.
174 valid values depends on the pingroup. See "DRVUP_SLWF" in the Tegra TRM.
Dpinctrl_spear.txt46 group. See the SPEAr's TRM to determine which are valid for each pin or group.
/Documentation/admin-guide/media/
Domap3isp.rst74 OMAP 3430 TRM:
78 OMAP 35xx TRM:
81 OMAP 3630 TRM:
85 DM 3730 TRM:
/Documentation/translations/zh_CN/video4linux/
Domap3isp.txt221 大多数域的解释可以在 OMAP 的 TRM 中找到。以下两个域对于以上所有的
222 私有 IOCTL 配置都很常见,由于他们没有在 TRM 中提及,故需要对其有
257 OMAP 3430 TRM:
261 OMAP 35xx TRM:
264 OMAP 3630 TRM:
268 DM 3730 TRM:
/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-dfll.txt40 - nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
41 - nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
42 - nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
43 - nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
44 - nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
47 - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
Dzynq-7000.txt7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
/Documentation/admin-guide/perf/
Darm-cmn.rst25 Most events are specified in a format based directly on the TRM
45 (as defined in the "Node ID Mapping" section of the TRM).
59 "wp_exclusive" are specified per the TRM definitions for dtm_wp_config0.
Darm_dsu_pmu.rst21 The user should refer to the TRM of the product to figure out the supported events
/Documentation/devicetree/bindings/memory-controllers/
Darm,pl35x-smc.yaml17 The TRM is available here:
119 # According to TRM, really should be 3 clocks
Dnvidia,tegra124-mc.yaml69 "15.6.1 MC Registers" in the TRM.
Dnvidia,tegra30-mc.yaml86 "18.13.1 MC Registers" in the TRM.
Dnvidia,tegra20-emc.yaml85 (see section "15.4.1 EMC Registers" in the TRM) whose values
/Documentation/devicetree/bindings/dma/
Dnvidia,tegra20-apbdma.txt16 select value for the peripheral. For more details, consult the Tegra TRM's
/Documentation/devicetree/bindings/mfd/
Dtwl4030-audio.txt19 -ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the
/Documentation/hwmon/
Dvexpress.rst17 * Section "4.4.14. System Configuration registers" of the V2M-P1 TRM:
/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
/Documentation/devicetree/bindings/perf/
Darm,cmn.yaml39 discovery node (see TRM definition of ROOTNODEBASE). Not
/Documentation/devicetree/bindings/devfreq/
Dnvidia,tegra30-actmon.yaml58 entry. Consult TRM documentation for information about available
/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml173 ti,trm-icp:
240 ti,trm-icp = <0x8>;
/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-etb1020 value stored in this register+1 (from ARM ETB-TRM).
/Documentation/devicetree/bindings/display/
Darm,malidp.yaml79 See the ARM Mali-DP500 TRM for details on the encoding.
/Documentation/devicetree/bindings/display/ti/
Dti,am65x-dss.yaml30 Addresses to each DSS memory region described in the SoC's TRM.
/Documentation/devicetree/bindings/bus/
Dnvidia,tegra20-gmi.txt53 From Tegra TRM:
/Documentation/devicetree/bindings/arm/
Dvexpress-config.yaml16 function and device numbers - see motherboard's TRM for more details.
/Documentation/userspace-api/media/drivers/
Domap3isp-uapi.rst168 are not part of the TRM.

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