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/Documentation/userspace-api/media/v4l/
Dpixfmt-srggb10-ipu3.rst20 sRGB / Bayer formats with 10 bits per sample with every 25 pixels packed
21 to 32 bytes leaving 6 most significant bits padding in the last byte.
40 - G\ :sub:`0001low`\ (bits 7--2)
42 B\ :sub:`0000high`\ (bits 1--0)
43 - B\ :sub:`0002low`\ (bits 7--4)
45 G\ :sub:`0001high`\ (bits 3--0)
46 - G\ :sub:`0003low`\ (bits 7--6)
48 B\ :sub:`0002high`\ (bits 5--0)
52 - G\ :sub:`0005low`\ (bits 7--2)
54 B\ :sub:`0004high`\ (bits 1--0)
[all …]
Dpixfmt-srggb14p.rst24 bits per colour. Every four consecutive samples are packed into seven
25 bytes. Each of the first four bytes contain the eight high order bits
27 significants bits of each pixel, in the same order.
63 - G\ :sub:`01low bits 1--0`\ (bits 7--6)
65 B\ :sub:`00low bits 5--0`\ (bits 5--0)
67 - B\ :sub:`02low bits 3--0`\ (bits 7--4)
69 G\ :sub:`01low bits 5--2`\ (bits 3--0)
71 - G\ :sub:`03low bits 5--0`\ (bits 7--2)
73 B\ :sub:`02low bits 5--4`\ (bits 1--0)
87 - R\ :sub:`11low bits 1--0`\ (bits 7--6)
[all …]
Dpixfmt-srggb10p.rst23 bits per sample. Every four consecutive samples are packed into 5
24 bytes. Each of the first 4 bytes contain the 8 high order bits
26 bits of each pixel, in the same order.
48 - G\ :sub:`03low`\ (bits 7--6) B\ :sub:`02low`\ (bits 5--4)
50 G\ :sub:`01low`\ (bits 3--2) B\ :sub:`00low`\ (bits 1--0)
56 - R\ :sub:`13low`\ (bits 7--6) G\ :sub:`12low`\ (bits 5--4)
58 R\ :sub:`11low`\ (bits 3--2) G\ :sub:`10low`\ (bits 1--0)
64 - G\ :sub:`23low`\ (bits 7--6) B\ :sub:`22low`\ (bits 5--4)
66 G\ :sub:`21low`\ (bits 3--2) B\ :sub:`20low`\ (bits 1--0)
72 - R\ :sub:`33low`\ (bits 7--6) G\ :sub:`32low`\ (bits 5--4)
[all …]
Dpixfmt-srggb12p.rst21 bits per colour. Every two consecutive samples are packed into three
22 bytes. Each of the first two bytes contain the 8 high order bits of
24 bits of each pixel, in the same order.
46 - G\ :sub:`01low`\ (bits 7--4)
48 B\ :sub:`00low`\ (bits 3--0)
51 - G\ :sub:`03low`\ (bits 7--4)
53 B\ :sub:`02low`\ (bits 3--0)
58 - R\ :sub:`11low`\ (bits 7--4)
60 G\ :sub:`10low`\ (bits 3--0)
63 - R\ :sub:`13low`\ (bits 3--2)
[all …]
Dpixfmt-cnf4.rst9 Depth sensor confidence information as a 4 bits per pixel packed array
20 Bits 0-3 of byte n refer to confidence value of depth pixel 2*n,
21 bits 4-7 to confidence value of depth pixel 2*n+1.
30 * - Y'\ :sub:`01[3:0]`\ (bits 7--4) Y'\ :sub:`00[3:0]`\ (bits 3--0)
31 - Y'\ :sub:`03[3:0]`\ (bits 7--4) Y'\ :sub:`02[3:0]`\ (bits 3--0)
Dpixfmt-packed-yuv.rst16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
18 denotes bits of the alpha component (if supported by the format), and 'X'
19 denotes padding bits.
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
31 order, and on the number of bits for each component. For instance the YUV565
150 For the YUV444 and YUV555 formats, the value of alpha bits is undefined
156 The next table lists the packed YUV 4:4:4 formats with 8 bits per component.
158 memory, and on the total number of bits per pixel. For instance, the VUYX32
257 - The padding bits contain undefined values that must be ignored by all
260 The next table lists the packed YUV 4:4:4 formats with 12 bits per component.
[all …]
/Documentation/devicetree/bindings/cpufreq/
Dvirtual,android-v-only-cpufreq.yaml72 opp64000 { opp-hz = /bits/ 64 <64000>; };
73 opp128000 { opp-hz = /bits/ 64 <128000>; };
74 opp192000 { opp-hz = /bits/ 64 <192000>; };
75 opp256000 { opp-hz = /bits/ 64 <256000>; };
76 opp320000 { opp-hz = /bits/ 64 <320000>; };
77 opp384000 { opp-hz = /bits/ 64 <384000>; };
78 opp425000 { opp-hz = /bits/ 64 <425000>; };
84 opp64000 { opp-hz = /bits/ 64 <64000>; };
85 opp128000 { opp-hz = /bits/ 64 <128000>; };
86 opp192000 { opp-hz = /bits/ 64 <192000>; };
[all …]
Dcpufreq-mediatek.txt41 opp-hz = /bits/ 64 <598000000>;
46 opp-hz = /bits/ 64 <747500000>;
51 opp-hz = /bits/ 64 <1040000000>;
56 opp-hz = /bits/ 64 <1196000000>;
61 opp-hz = /bits/ 64 <1300000000>;
101 opp-hz = /bits/ 64 <507000000>;
106 opp-hz = /bits/ 64 <702000000>;
111 opp-hz = /bits/ 64 <1001000000>;
116 opp-hz = /bits/ 64 <1105000000>;
121 opp-hz = /bits/ 64 <1183000000>;
[all …]
/Documentation/userspace-api/media/rc/
Drc-protos.rst32 This IR protocol uses manchester encoding to encode 14 bits. There is a
38 .. flat-table:: rc5 bits scancode mapping
81 done to keep it compatible with plain rc-5 where there are two start bits.
88 .. flat-table:: rc-5-sz bits scancode mapping
91 * - rc-5-sz bits
130 This rc-5 extended to encoded 20 bits. The is a 3555 microseconds space
133 .. flat-table:: rc-5x-20 bits scancode mapping
136 * - rc-5-sz bits
185 The scancode is a 16 bits value, where the address is the lower 8 bits
186 and the command the higher 8 bits; this is reversed from IR order.
[all …]
/Documentation/devicetree/bindings/input/touchscreen/
Dad7879.txt18 This property has to be a '/bits/ 8' value
23 This property has to be a '/bits/ 8' value
28 This property has to be a '/bits/ 8' value
33 This property has to be a '/bits/ 8' value
36 This property has to be a '/bits/ 8' value
48 adi,first-conversion-delay = /bits/ 8 <3>;
49 adi,acquisition-time = /bits/ 8 <1>;
50 adi,median-filter-size = /bits/ 8 <2>;
51 adi,averaging = /bits/ 8 <1>;
52 adi,conversion-interval = /bits/ 8 <255>;
[all …]
/Documentation/filesystems/ext4/
Dgroup_descr.rst38 checksum is the lower 16 bits of the checksum of the FS UUID, the group
56 - Lower 32-bits of location of block bitmap.
60 - Lower 32-bits of location of inode bitmap.
64 - Lower 32-bits of location of inode table.
68 - Lower 16-bits of free block count.
72 - Lower 16-bits of free inode count.
76 - Lower 16-bits of directory count.
84 - Lower 32-bits of location of snapshot exclusion bitmap.
88 - Lower 16-bits of the block bitmap checksum.
92 - Lower 16-bits of the inode bitmap checksum.
[all …]
Dinodes.rst47 - Lower 16-bits of Owner UID.
51 - Lower 32-bits of size in bytes.
63 value and this field contains the lower 32 bits of the attribute value's
79 - Lower 16-bits of GID.
93 - Lower 32-bits of “block” count. If the huge_file feature flag is not
120 - Lower 32-bits of extended attribute block. ACLs are of course one of
126 - Upper 32-bits of file/directory size. In ext2/3 this field was named
144 - Upper 16-bits of the inode checksum.
148 - Extra change time bits. This provides sub-second precision. See Inode
153 - Extra modification time bits. This provides sub-second precision.
[all …]
/Documentation/devicetree/bindings/leds/
Dleds-lp55xx.yaml174 clock-mode = /bits/ 8 <2>;
175 pwr-sel = /bits/ 8 <3>; /* D1~9 connected to VOUT */
181 led-cur = /bits/ 8 <0x14>;
182 max-cur = /bits/ 8 <0x20>;
188 led-cur = /bits/ 8 <0x14>;
189 max-cur = /bits/ 8 <0x20>;
195 led-cur = /bits/ 8 <0x14>;
196 max-cur = /bits/ 8 <0x20>;
202 led-cur = /bits/ 8 <0x14>;
203 max-cur = /bits/ 8 <0x20>;
[all …]
/Documentation/devicetree/bindings/interconnect/
Dmediatek,cci.yaml79 opp-hz = /bits/ 64 <273000000>;
83 opp-hz = /bits/ 64 <338000000>;
87 opp-hz = /bits/ 64 <403000000>;
91 opp-hz = /bits/ 64 <463000000>;
95 opp-hz = /bits/ 64 <546000000>;
99 opp-hz = /bits/ 64 <624000000>;
103 opp-hz = /bits/ 64 <689000000>;
107 opp-hz = /bits/ 64 <767000000>;
111 opp-hz = /bits/ 64 <845000000>;
115 opp-hz = /bits/ 64 <871000000>;
[all …]
/Documentation/devicetree/bindings/nvmem/
Dsocionext,uniphier-efuse.yaml45 bits = <4 2>;
49 bits = <4 2>;
53 bits = <4 2>;
57 bits = <4 2>;
61 bits = <0 4>;
65 bits = <0 4>;
69 bits = <0 4>;
73 bits = <0 4>;
77 bits = <0 4>;
81 bits = <0 4>;
Dmediatek,efuse.yaml61 bits = <0 5>;
65 bits = <5 5>;
69 bits = <2 6>;
73 bits = <0 5>;
77 bits = <5 5>;
81 bits = <2 6>;
85 bits = <0 5>;
89 bits = <5 5>;
/Documentation/devicetree/bindings/leds/backlight/
Dlp855x-backlight.yaml91 dev-ctrl = /bits/ 8 <0x00>;
98 rom-addr = /bits/ 8 <0x14>;
99 rom-val = /bits/ 8 <0xcf>;
104 rom-addr = /bits/ 8 <0x15>;
105 rom-val = /bits/ 8 <0xc7>;
110 rom-addr = /bits/ 8 <0x19>;
111 rom-val = /bits/ 8 <0x0f>;
125 dev-ctrl = /bits/ 8 <0x85>;
126 init-brt = /bits/ 8 <0x10>;
140 dev-ctrl = /bits/ 8 <0x41>;
[all …]
/Documentation/devicetree/bindings/net/
Dmicrel.txt10 bits that are currently supported:
12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
/Documentation/leds/
Dleds-mlxcpld.rst29 - Bits [3:0]
33 - Bits [7:4]
37 - Bits [3:0]
41 - Bits [7:4]
45 - Bits [3:0]
49 - Bits [7:4]
78 - Bits [3:0]
82 - Bits [3:0]
86 - Bits [3:0]
90 - Bits [7:4]
[all …]
/Documentation/devicetree/bindings/ata/
Dceva,ahci-1v84.yaml45 ceva,p0-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
57 ceva,p0-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
69 ceva,p0-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
81 ceva,p0-retry-params = /bits/ 16 <RIT RCT>;
91 ceva,p1-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
103 ceva,p1-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
115 ceva,p1-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
127 ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
178 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
179 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
[all …]
/Documentation/staging/
Dcrc32.rst22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
26 Note that a CRC is computed over a string of *bits*, so you have
27 to decide on the endianness of the bits within each byte. To get
56 But also notice how the next_input_bit() bits we're shifting into
58 32 bits later. Thus, the first 32 cycles of this are pretty boring.
65 can be precomputed, and merging in the final 32 zero bits to make room
87 As long as next_input_bit is returning the bits in a sensible order, we don't
88 *have* to wait until the last possible moment to merge in additional bits.
89 We can do it 8 bits at a time rather than 1 bit at a time::
109 If the input is a multiple of 32 bits, you can even XOR in a 32-bit
[all …]
/Documentation/virt/kvm/devices/
Dxics.rst40 64 bits of state which can be read and written using the
45 * Unused, 16 bits
47 * Pending interrupt priority, 8 bits
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
53 * Pending interrupt source number, 24 bits
56 * Current processor priority, 8 bits
60 Each source has 64 bits of state that can be read and written using
66 * Destination (server number), 32 bits
71 * Priority, 8 bits
/Documentation/devicetree/bindings/spi/
Dspi-xilinx.yaml28 xlnx,num-ss-bits:
33 xlnx,num-transfer-bits:
34 description: Number of bits per transfer. This will be 8 if not specified.
52 xlnx,num-ss-bits = <0x1>;
53 xlnx,num-transfer-bits = <32>;
/Documentation/admin-guide/mm/
Dsoft-dirty.rst8 1. Clear soft-dirty bits from the task's PTEs.
15 3. Read soft-dirty bits from the PTEs.
28 soft-dirty bits clear, the #PF-s that occur after that are processed fast.
31 bits on the PTE.
34 there is still a scenario when we can lose soft dirty bits -- a task
37 including soft dirty bits. To notify user space application about such
/Documentation/driver-api/iio/
Dbuffers.rst29 called a scan element. The important bits configuring scan elements are
40 Format is [be|le]:[s|u]bits/storagebits[Xrepeat][>>shift] .
44 * *bits*, is the number of valid data bits.
45 * *storagebits*, is the number of bits (after padding) that it occupies in the
47 * *repeat*, specifies the number of bits/storagebits repetitions. When the
50 masking out unused bits.
53 data is stored in two 8-bits registers as follows::
71 two byte little endian signed data, that needs a 4 bits right shift before
72 masking out the 12 valid bits of data.

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