Searched full:channel (Results 1 – 25 of 904) sorted by relevance
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
24 - interrupts : interrupt specifier for DMA channel IRQ
38 dma-channel@0 {
39 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 dma-channel@80 {
46 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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| /Documentation/sound/designs/ |
| D | channel-mapping-api.rst | 2 ALSA PCM channel-mapping API
10 The channel mapping API allows user to query the possible channel maps
11 and the current channel map, also optionally to modify the channel map
14 A channel map is an array of position for each PCM channel.
15 Typically, a stereo PCM stream has a channel map of
17 while a 4.0 surround PCM stream has a channel map of
20 The problem, so far, was that we had no standard channel map
21 explicitly, and applications had no way to know which channel
29 was no way to specify this because of lack of channel map
30 specification. These are the main motivations for the new channel
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ad5770r.yaml | 58 channel@0:
59 description: Represents an external channel which are
60 connected to the DAC. Channel 0 can act both as a current
67 description: This represents the channel number.
71 description: Output range of the channel.
83 channel@1:
84 description: Represents an external channel which are
91 description: This represents the channel number.
95 description: Output range of the channel.
100 channel@2:
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| D | adi,ad5755.yaml | 7 title: Analog Devices AD5755 Multi-Channel DAC
40 1: Channel A and Channel B clock on the same edge,
41 Channel C and Channel D clock on opposite edges.
42 2: Channel A and Channel C clock on the same edge,
43 Channel B and Channel D clock on opposite edges.
44 3: Channel A, Channel B, Channel C, and Channel D
61 "#io-channel-cells":
69 "^channel@[0-7]$":
71 description: Child node to describe a channel
143 channel@0 {
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| /Documentation/networking/ |
| D | ppp_generic.rst | 4 PPP Generic Driver and Channel Interface
26 the services of PPP ``channels``. A PPP channel encapsulates a
28 PPP channel implementation can be arbitrarily complex internally but
31 handle ioctl requests. Currently there are PPP channel
36 natural and straightforward way, by allowing more than one channel to
42 PPP channel API
49 Each channel has to provide two functions to the generic PPP layer,
53 send. The channel has the option of rejecting the frame for
55 and the channel should call the ppp_output_wakeup() function at a
61 program to control aspects of the channel's behaviour. This
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| /Documentation/ABI/testing/ |
| D | configfs-most | 19 configure the buffer size for this channel
22 configure the sub-buffer size for this channel
28 channel
32 this channel
51 channel
52 name of the channel the link is to be attached to
74 configure the buffer size for this channel
77 configure the sub-buffer size for this channel
83 channel
87 this channel
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| D | sysfs-bus-rpmsg | 6 Every rpmsg device is a communication channel with a remote
11 This sysfs entry contains the name of this channel.
18 Every rpmsg device is a communication channel with a remote
21 starts listening on one end of a channel, it assigns it with
27 of this channel. If it contains 0xffffffff, then an address
29 channel).
36 Every rpmsg device is a communication channel with a remote
39 starts listening on one end of a channel, it assigns it with
45 of this channel. If it contains 0xffffffff, then an address
47 is attached to this channel is exposing a service to the
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| D | sysfs-bus-most | 152 What: /sys/bus/most/devices/<dev>/<channel>/
157 For every channel of the device a directory is created, whose
159 collect information about the channel's capabilities and
163 What: /sys/bus/most/devices/<dev>/<channel>/available_datatypes
168 Indicates the data types the channel can transport.
171 What: /sys/bus/most/devices/<dev>/<channel>/available_directions
176 Indicates the directions the channel is capable of.
179 What: /sys/bus/most/devices/<dev>/<channel>/number_of_packet_buffers
184 Indicates the number of packet buffers the channel can
188 What: /sys/bus/most/devices/<dev>/<channel>/number_of_stream_buffers
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | qcom,pm8018-adc.yaml | 44 a hardware channel on all systems.
49 "#io-channel-cells":
59 - "#io-channel-cells"
62 - adc-channel@c
63 - adc-channel@d
64 - adc-channel@f
67 "^(adc-channel@)[0-9a-f]$":
70 ADC channel specific configuration.
92 Channel calibration type. If this property is specified
93 VADC will use a special voltage references for channel
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| D | renesas,rzg2l-adc.yaml | 16 stored in a 32-bit data register corresponding to each channel.
71 "^channel@[0-7]$":
80 The channel number.
95 "^channel@[2-7]$": false
96 "^channel@[0-1]$":
103 "^channel@[0-7]$":
131 channel@0 {
134 channel@1 {
137 channel@2 {
140 channel@3 {
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| D | st,stm32-dfsdm-adc.yaml | 96 - For st,stm32-dfsdm-dmic: 1 channel numbered from 0 to 7.
102 st,adc-channel-names:
103 description: List of single-ended channel names.
114 "#io-channel-cells":
117 st,adc-channel-types:
119 Single-ended channel input type.
128 st,adc-channel-clk-src:
139 st,adc-alt-channel:
143 If not set, channel n is connected to SPI input n.
144 If set, channel n is connected to SPI input n + 1.
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| D | ti,tsc2046.yaml | 29 "#io-channel-cells":
43 "^channel@[0-7]$":
50 The channel number. It can have up to 8 channels
80 #io-channel-cells = <1>;
85 channel@0 {
88 channel@1 {
93 channel@2 {
96 channel@3 {
101 channel@4 {
106 channel@5 {
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| /Documentation/devicetree/bindings/iio/multiplexer/ |
| D | io-channel-mux.yaml | 4 $id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml#
7 title: I/O channel multiplexer
14 e.g. an ADC channel, these bindings describe that situation.
16 For each non-empty string in the channels property, an io-channel will be
17 created. The number of this io-channel is the same as the index into the list
25 const: io-channel-mux
29 description: Channel node of the parent channel that has multiplexed input.
31 io-channel-names:
41 string for a state means that the channel is not available.
48 "#io-channel-cells":
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| /Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 2 It can be configured to have one channel or two channels. If configured
7 target devices. It can be configured to have one channel or two channels.
28 - dma-channel child node: Should have at least one channel and can have up to
30 DMA channel (see child node properties below).
59 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
62 {2}, flush mm2s channel
63 {3}, flush s2mm channel
67 For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
68 "xlnx,axi-vdma-s2mm-channel".
69 For CDMA: It should be "xlnx,axi-cdma-channel".
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| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr-channel.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
24 - jedec,lpddr5-channel
28 The number of DQ pins in the channel. If this number is different
31 channel (with the channel's DQ pins split up between the different
34 channel is equal to the sum of the densities of each rank on the
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| /Documentation/devicetree/bindings/firmware/ |
| D | fsl,scu.yaml | 52 channel for general interrupt. The number of expected tx and rx
61 - description: TX0 MU channel
62 - description: RX0 MU channel
64 - description: TX0 MU channel
65 - description: RX0 MU channel
66 - description: optional MU channel for general interrupt
68 - description: TX0 MU channel
69 - description: TX1 MU channel
70 - description: TX2 MU channel
71 - description: TX3 MU channel
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| /Documentation/devicetree/bindings/dma/ |
| D | stericsson,dma40.yaml | 19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
42 20: SLIMbus or HSI channel 0
43 21: SLIMbus or HSI channel 1
44 22: SLIMbus or HSI channel 2
45 23: SLIMbus or HSI channel 3
53 31: MSP port 0 or SLIMbus channel 0
68 46: SLIMbus channel 8 or Multimedia DSP SXA6
69 47: SLIMbus channel 9 or Multimedia DSP SXA7
74 52: SLIMbus or HSI channel 4
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| D | k3dma.txt | 10 - interrupts: Should contain one interrupt shared by all channel
13 - dma-requests: virtual channels supported, each virtual channel
32 For example, i2c0 read channel request line is 18, while write channel use 19
36 dmas = <&dma0 18 /* read channel */
37 &dma0 19>; /* write channel */
43 dmas = <&dma0 20 /* read channel */
44 &dma0 21>; /* write channel */
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| /Documentation/devicetree/bindings/sound/ |
| D | st,sta32x.txt | 27 0: 2-channel (full-bridge) power, 2-channel data-out
29 2: 2 Channel (Full-Bridge) Power, 1 Channel FFX
30 3: 1 Channel Mono-Parallel
34 - st,ch1-output-mapping: Channel 1 output mapping
35 - st,ch2-output-mapping: Channel 2 output mapping
36 - st,ch3-output-mapping: Channel 3 output mapping
37 0: Channel 1
38 1: Channel 2
39 2: Channel 3
40 If parameter is missing, channel 1 is chosen.
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| D | tlv320adcx140.yaml | 8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
70 0 - (default) Odd channel is latched on the negative edge and even
71 channel is latched on the positive edge.
72 1 - Odd channel is latched on the positive edge and even channel is
75 PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
76 PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
77 PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
78 PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
96 4 - GPIX is configured as a PDM data input for channel 1 and channel
98 5 - GPIX is configured as a PDM data input for channel 3 and channel
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| D | sprd-mcdt.txt | 1 Spreadtrum Multi-Channel Data Transfer Binding
3 The Multi-channel data transfer controller is used for sound stream
5 supports 10 DAC channel and 10 ADC channel, and each channel can be
11 - interrupts: Should contain one interrupt shared by all channel.
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| /Documentation/arch/arm/stm32/ |
| D | stm32-dma-mdma-chaining.rst | 58 channel is null. The channel transfer complete of the last node is the end of
64 resources and bus congestion. Transfer Complete signal of STM32 DMA channel
77 | Channel *0* | DMA1 channel 0 | dma1_tcf0 | *0x00* |
79 | Channel *1* | DMA1 channel 1 | dma1_tcf1 | *0x01* |
81 | Channel *2* | DMA1 channel 2 | dma1_tcf2 | *0x02* |
83 | Channel *3* | DMA1 channel 3 | dma1_tcf3 | *0x03* |
85 | Channel *4* | DMA1 channel 4 | dma1_tcf4 | *0x04* |
87 | Channel *5* | DMA1 channel 5 | dma1_tcf5 | *0x05* |
89 | Channel *6* | DMA1 channel 6 | dma1_tcf6 | *0x06* |
91 | Channel *7* | DMA1 channel 7 | dma1_tcf7 | *0x07* |
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| /Documentation/filesystems/ |
| D | relay.rst | 11 A 'relay channel' is a kernel->user data relay mechanism implemented
12 as a set of per-cpu kernel buffers ('channel buffers'), each
14 clients write into the channel buffers using efficient write
15 functions; these automatically log into the current cpu's channel
19 are associated with the channel buffers using the API described below.
21 The format of the data logged into the channel buffers is completely
35 Each relay channel has one buffer per CPU, each buffer has one or more
50 A relay channel can operate in a mode where it will overwrite data not
53 The relay channel itself does not provide for communication of such
61 the channel buffers, special-purpose communication between kernel and
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| /Documentation/trace/coresight/ |
| D | coresight-ect.rst | 21 0 C 0----------->: : +======>(other CTI channel IO)
31 channels. When an input trigger becomes active, the attached channel will
32 become active. Any output trigger attached to that channel will also
33 become active. The active channel is propagated to other CTIs via the CTM,
35 channel gate.
37 It is also possible to activate a channel using system software directly
43 no programmed trigger/channel attachments, so will not affect the system
89 * ``channels``: Contains the channel API - CTI main programming interface.
158 Attaches trigout(1) to channel(0), then activates channel(0) generating a
164 * ``trigin_attach, trigout_attach``: Attach a channel to a trigger signal.
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| /Documentation/i2c/ |
| D | i2c-sysfs.rst | 85 an abstraction of a channel behind an I2C MUX. In case it is an abstraction of a
86 MUX channel, whenever we access an I2C device via a such logical bus, the kernel
87 will switch the I2C MUX for you to the proper channel as part of the
123 `-- 7-0071 (4-channel I2C MUX at 0x71)
124 |-- i2c-60 (channel-0)
125 |-- i2c-73 (channel-1)
128 | `-- 73-0072 (8-channel I2C MUX at 0x72)
129 | |-- i2c-78 (channel-0)
130 | |-- ... (channel-1...6, i2c-79...i2c-84)
131 | `-- i2c-85 (channel-7)
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