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/Documentation/devicetree/bindings/i2c/
Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
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Di2c-axxia.txt4 - compatible : Must be "lsi,api2c"
5 - reg : Offset and length of the register set for the device
6 - interrupts : the interrupt specifier
7 - #address-cells : Must be <1>;
8 - #size-cells : Must be <0>;
9 - clock-names : Must contain "i2c".
10 - clocks: Must contain an entry for each name in clock-names. See the common
11 clock bindings.
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
15 the default 100 kHz frequency will be used. As only Normal and Fast modes
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Di2c-img-scb.txt4 - compatible: "img,scb-i2c"
5 - reg: Physical base address and length of controller registers
6 - interrupts: Interrupt number used by the controller
7 - clocks : Should contain a clock specifier for each entry in clock-names
8 - clock-names : Should contain the following entries:
9 "scb", for the SCB core clock.
10 "sys", for the system clock.
11 - clock-frequency: The I2C bus frequency in Hz
12 - #address-cells: Should be <1>
13 - #size-cells: Should be <0>
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Di2c-sprd.txt4 - compatible: Should be "sprd,sc9860-i2c".
5 - reg: Specify the physical base address of the controller and length
7 - interrupts: Should contain I2C interrupt.
8 - clock-names: Should contain following entries:
9 "i2c" for I2C clock,
10 "source" for I2C source (parent) clock,
11 "enable" for I2C module enable clock.
12 - clocks: Should contain a clock specifier for each entry in clock-names.
13 - clock-frequency: Contains desired I2C bus clock frequency in Hz.
14 - #address-cells: Should be 1 to describe address cells for I2C device address.
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/Documentation/devicetree/bindings/clock/
Dsilabs,si570.txt2 I2C clock generators.
5 This binding uses the common clock binding[1]. Details about the devices can be
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
15 - compatible: Shall be one of "silabs,si570", "silabs,si571",
17 - reg: I2C device address.
18 - #clock-cells: From common clock bindings: Shall be 0.
19 - factory-fout: Factory set default frequency. This frequency is part specific.
20 The correct frequency for the part used has to be provided in
23 - temperature-stability: Temperature stability of the device in PPM. Should be
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Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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Dallwinner,sun4i-a10-osc-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Gateable Oscillator Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun4i-a10-osc-clk
25 clock-frequency:
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Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
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Dclps711x-clock.txt1 * Clock bindings for the Cirrus Logic CLPS711X CPUs
4 - compatible : Shall contain "cirrus,ep7209-clk".
5 - reg : Address of the internal register set.
6 - startup-frequency: Factory set CPU startup frequency in HZ.
7 - #clock-cells : Should be <1>.
9 The clock consumer should specify the desired clock by having the clock
10 ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
11 for the full list of CLPS711X clock IDs.
15 #clock-cells = <1>;
16 compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
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Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
18 the clock source programming and most of the clock dividers.
20 CLKGEN input signals include the external clock for the reference frequency
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Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
15 const: fixed-clock
17 "#clock-cells":
20 clock-frequency: true
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Dfsl,plldig.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
30 fsl,vco-hz:
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Dpwm-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/pwm-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: An external clock signal driven by a PWM pin.
10 - Philipp Zabel <p.zabel@pengutronix.de>
14 const: pwm-clock
16 '#clock-cells':
19 clock-frequency:
20 description: Exact output frequency, in case the PWM period is not exact
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Dsamsung,exynos-ext-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC external/osc/XXTI/XusbXTI clock
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.
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/Documentation/devicetree/bindings/spi/
Dspi-sc18is602.txt4 - compatible : Should be one of
8 - reg: I2C bus address
11 - clock-frequency : external oscillator clock frequency. If not
12 specified, the SC18IS602 default frequency (7372000) will be used.
14 The clock-frequency property is relevant and needed only if the chip has an
22 clock-frequency = <14744000>;
Dspi_oc_tiny.txt4 - compatible : should be "opencores,tiny-spi-rtlsvn2".
5 - gpios : should specify GPIOs used for chipselect.
7 - clock-frequency : input clock frequency to the core.
8 - baud-width: width, in bits, of the programmable divider used to scale
9 the input clock to SCLK.
11 The clock-frequency and baud-width properties are needed only if the divider
/Documentation/devicetree/bindings/media/i2c/
Daptina,mt9p031.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
15 simple two-wire serial interface.
20 - aptina,mt9p006
21 - aptina,mt9p031
22 - aptina,mt9p031m
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Dtoshiba,et8ek8.txt6 Documentation/devicetree/bindings/media/video-interfaces.txt .
10 --------------------
12 - compatible: "toshiba,et8ek8"
13 - reg: I2C address (0x3e, or an alternative address)
14 - vana-supply: Analogue voltage supply (VANA), 2.8 volts
15 - clocks: External clock to the sensor
16 - clock-frequency: Frequency of the external clock to the sensor. Camera
17 driver will set this frequency on the external clock. The clock frequency is
18 a pre-determined frequency known to be suitable to the board.
19 - reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
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/Documentation/devicetree/bindings/net/wireless/
Dti,wlcore.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 Note that the *-clock-frequency properties assume internal clocks. In case
15 of external clocks, new bindings (for parsing the clock nodes) have to be
21 - ti,wl1271
22 - ti,wl1273
23 - ti,wl1281
24 - ti,wl1283
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/Documentation/devicetree/bindings/net/can/
Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
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/Documentation/devicetree/bindings/display/bridge/
Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
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/Documentation/devicetree/bindings/iio/frequency/
Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
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/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
28 - const: dmc_clk
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/Documentation/devicetree/bindings/iio/imu/
Dadi,adis16480.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - adi,adis16375
16 - adi,adis16480
17 - adi,adis16485
18 - adi,adis16488
19 - adi,adis16490
20 - adi,adis16495-1
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/Documentation/ABI/testing/
Dsysfs-driver-habanalabs21 Description: Allows the user to set the maximum clock frequency, in MHz.
22 The device clock might be set to lower value than the maximum.
24 frequency value of the device clock. This property is valid
31 Description: Displays the current frequency, in MHz, of the device clock.
64 on-board EEPROM
82 Description: Interface to trigger a hard-reset operation for the device.
83 Hard-reset will reset ALL internal components of the device
90 Description: Displays how many times the device have undergone a hard-reset
97 Description: Allows the user to set the maximum clock frequency for MME, TPC
105 Description: Allows the user to set the maximum clock frequency, in Hz, of
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