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/Documentation/devicetree/bindings/clock/
Dmvebu-core-clock.txt1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
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Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
26 containing clock control registers
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Dsocionext,uniphier-clock.yaml4 $id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
7 title: UniPhier clock controller
15 - description: System clock
17 - socionext,uniphier-ld4-clock
18 - socionext,uniphier-pro4-clock
19 - socionext,uniphier-sld8-clock
20 - socionext,uniphier-pro5-clock
21 - socionext,uniphier-pxs2-clock
22 - socionext,uniphier-ld6b-clock
23 - socionext,uniphier-ld11-clock
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Dqcom,gcc-sm8350.yaml4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8350
13 Qualcomm global clock control module provides the clocks, resets and power
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source (Optional clock)
27 - description: PCIE 1 Pipe clock source (Optional clock)
28 - description: UFS card Rx symbol 0 clock source (Optional clock)
29 - description: UFS card Rx symbol 1 clock source (Optional clock)
30 - description: UFS card Tx symbol 0 clock source (Optional clock)
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Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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Dqcom,mmcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller
14 Qualcomm multimedia clock control module provides the clocks, resets and
37 clock-names:
41 '#clock-cells':
55 Protected clock specifier list as per common clock binding
64 - '#clock-cells'
83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
85 - description: DSI phy instance 1 dsi clock
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Dtesla,fsd-clock.yaml4 $id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
7 title: Tesla FSD (Full Self-Driving) SoC clock controller
14 FSD clock controller consist of several clock management unit
16 The root clock comes from external OSC clock (24 MHz).
19 'dt-bindings/clock/fsd-clk.h' header.
24 - tesla,fsd-clock-cmu
25 - tesla,fsd-clock-imem
26 - tesla,fsd-clock-peric
27 - tesla,fsd-clock-fsys0
28 - tesla,fsd-clock-fsys1
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Dsamsung,s3c64xx-clock.txt1 * Samsung S3C64xx Clock Controller
3 The S3C64xx clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
10 - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11 - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume. Some of the clocks are available only
23 dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
29 that they are defined using standard clock bindings with following
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Dsamsung,exynos5260-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
7 title: Samsung Exynos5260 SoC clock controller
18 - "fin_pll" - PLL input clock from XXTI
19 - "xrtcxti" - input clock from XRTCXTI
20 - "ioclk_pcm_extclk" - pcm external operation clock
21 - "ioclk_spdif_extclk" - spdif external operation clock
22 - "ioclk_i2s_cdclk" - i2s0 codec clock
26 are fed into the clock controller and then routed to the hardware blocks.
28 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
29 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
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Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
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Dpistachio-clock.txt1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
25 - reg: Must contain the base address and length of the core clock controller.
26 - #clock-cells: Must be 1. The single cell is the clock identifier.
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Dqcom,gcc-sm8450.yaml4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8450
13 Qualcomm global clock control module provides the clocks, resets and power
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source (Optional clock)
27 - description: PCIE 1 Pipe clock source (Optional clock)
28 - description: PCIE 1 Phy Auxiliary clock source (Optional clock)
29 - description: UFS Phy Rx symbol 0 clock source (Optional clock)
30 - description: UFS Phy Rx symbol 1 clock source (Optional clock)
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Dsamsung,exynos7-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
7 title: Samsung Exynos7 SoC clock controller
18 - "fin_pll" - PLL input clock from XXTI
21 include/dt-bindings/clock/exynos7-clk.h header.
26 - samsung,exynos7-clock-topc
27 - samsung,exynos7-clock-top0
28 - samsung,exynos7-clock-top1
29 - samsung,exynos7-clock-ccore
30 - samsung,exynos7-clock-peric0
31 - samsung,exynos7-clock-peric1
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Dimx7ulp-scg-clock.yaml4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
20 and and the Fast IRC clock (FIRCLK), clock sources and clock
23 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
26 Note: this binding doc is only for A7 clock domain.
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Dimx7ulp-pcc-clock.yaml4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
20 and and the Fast IRC clock (FIRCLK), clock sources and clock
23 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
26 Note: this binding doc is only for A7 clock domain.
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Dqcom,gcc-sc8280xp.yaml4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SC8280xp
13 Qualcomm global clock control module provides the clocks, resets and
16 See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
24 - description: XO reference clock
25 - description: Sleep clock
26 - description: UFS memory first RX symbol clock
27 - description: UFS memory second RX symbol clock
28 - description: UFS memory first TX symbol clock
29 - description: UFS card first RX symbol clock
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Dvt8500.txt1 Device Tree Clock bindings for arch-vt8500
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
17 - clocks : shall be the input parent clock phandle for the clock. This should
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Dsamsung,exynos850-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
7 title: Samsung Exynos850 SoC clock controller
17 Exynos850 clock controller is comprised of several CMU units, generating
19 tree nodes, and might depend on each other. Root clocks in that clock tree are
26 Each clock is assigned an identifier and client nodes can use this identifier
27 to specify the clock which they consume. All clocks available for usage
28 in clock consumer nodes are defined as preprocessor macros in
29 'dt-bindings/clock/exynos850.h' header.
50 clock-names:
54 "#clock-cells":
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Dsamsung,exynosautov9-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
7 title: Samsung Exynos Auto v9 SoC clock controller
17 Exynos Auto v9 clock controller is comprised of several CMU units, generating
19 tree nodes, and might depend on each other. Root clocks in that clock tree are
21 The external OSCCLK must be defined as fixed-rate clock in dts.
27 Each clock is assigned an identifier and client nodes can use this identifier
28 to specify the clock which they consume. All clocks available for usage
29 in clock consumer nodes are defined as preprocessor macros in
30 'include/dt-bindings/clock/samsung,exynosautov9.h' header.
49 clock-names:
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Dxlnx,versal-clk.yaml4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
7 title: Xilinx Versal clock controller
13 The clock controller is a hardware block of Xilinx versal clock tree. It
14 reads required input clock frequencies from the devicetree and acts as clock
15 provider for all clock consumers of PS clocks.
28 "#clock-cells":
32 description: List of clock specifiers which are external input
33 clocks to the given clock controller.
37 clock-names:
43 - "#clock-cells"
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Dstericsson,u8500-clks.yaml4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
19 clock controller) clocks. For some reason PRCC 4 does not exist so
37 prcmu-clock:
38 description: A subnode with one clock cell for PRCMU (power, reset, control
39 management unit) clocks. The cell indicates which PRCMU clock in the
40 prcmu-clock node the consumer wants to use.
44 '#clock-cells':
49 prcc-periph-clock:
50 description: A subnode with two clock cells for PRCC (peripheral
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Dsamsung,exynos7885-clock.yaml4 $id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
7 title: Samsung Exynos7885 SoC clock controller
17 Exynos7885 clock controller is comprised of several CMU units, generating
19 tree nodes, and might depend on each other. The root clock in that root tree
20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
21 as a fixed-rate clock in dts.
26 Each clock is assigned an identifier and client nodes can use this identifier
27 to specify the clock which they consume. All clocks available for usage
28 in clock consumer nodes are defined as preprocessor macros in
29 'dt-bindings/clock/exynos7885.h' header.
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/Documentation/devicetree/bindings/clock/ti/
Dgate.txt1 Binding for Texas Instruments gate clock.
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 is provided for this clock, the code assumes that a clockdomain
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
14 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
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Dinterface.txt1 Binding for Texas Instruments interface clock.
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 companion clock finding (match corresponding functional gate
9 clock) and hardware autoidle enable / disable.
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
16 "ti,omap3-interface-clock" - basic OMAP3 interface clock
17 "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
18 capability for waiting clock to be ready
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/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt8195-clock.yaml4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
13 The clock architecture in Mediatek like below
18 clock gate
20 The devices except apusys_pll provide clock gate control in different IP blocks.
55 '#clock-cells':
66 scp_adsp: clock-controller@10720000 {
69 #clock-cells = <1>;
73 imp_iic_wrap_s: clock-controller@11d03000 {
76 #clock-cells = <1>;
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