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/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
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Dcirrus,clps711x-fb.txt8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
10 Additionally, the display node has to define properties:
25 display = <&display>;
28 display: display {
33 display-timings {
Dallwinner,sun4i-a10-display-frontend.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml#
7 title: Allwinner A10 Display Engine Frontend
14 The display engine frontend does formats conversion, scaling,
20 - allwinner,sun4i-a10-display-frontend
21 - allwinner,sun5i-a13-display-frontend
22 - allwinner,sun6i-a31-display-frontend
23 - allwinner,sun7i-a20-display-frontend
24 - allwinner,sun8i-a23-display-frontend
25 - allwinner,sun8i-a33-display-frontend
26 - allwinner,sun9i-a80-display-frontend
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Dallwinner,sun4i-a10-display-backend.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
7 title: Allwinner A10 Display Engine Backend
14 The display engine backend exposes layers and sprites to the system.
19 - allwinner,sun4i-a10-display-backend
20 - allwinner,sun5i-a13-display-backend
21 - allwinner,sun6i-a31-display-backend
22 - allwinner,sun7i-a20-display-backend
23 - allwinner,sun8i-a23-display-backend
24 - allwinner,sun8i-a33-display-backend
25 - allwinner,sun9i-a80-display-backend
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Dxylon,logicvc-display.yaml5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
8 title: Xylon LogiCVC display controller
14 The Xylon LogiCVC is a display controller that supports multiple layers.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
67 xylon,display-interface:
79 description: Display output interface (C_DISPLAY_INTERFACE).
81 xylon,display-colorspace:
89 description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
91 xylon,display-depth:
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Dintel,keembay-display.yaml4 $id: http://devicetree.org/schemas/display/intel,keembay-display.yaml#
7 title: Intel Keem Bay display controller
15 const: intel,keembay-display
40 description: Display output node to DSI.
58 display@20930000 {
59 compatible = "intel,keembay-display";
/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst5 On this page, we try to keep track of acronyms related to the display
37 * DISPCLK: Display Clock
39 * DCFCLK: Display Controller Fabric Clock
56 Display Abstraction layer
59 Display Core
62 Display Controller
68 Display Controller Engine
71 Display Controller HUB
80 Display Core Next
83 Display Clock Generator block
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Dindex.rst1 .. _amdgpu-display-core:
4 drm/amd/display - Display Core (DC)
7 AMD display engine is partially shared with other operating systems; for this
8 reason, our Display Core Driver is divided into two pieces:
10 1. **Display Core (DC)** contains the OS-agnostic components. Things like
12 2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
15 The display pipe is responsible for "scanning out" a rendered frame from the
16 GPU memory (also called VRAM, FrameBuffer, etc.) to a display. In other words,
28 display-manager.rst
/Documentation/devicetree/bindings/auxdisplay/
Dmodtronix,lcd2s.yaml7 title: Modtronix engineering LCD2S Character LCD Display
13 The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
14 The display supports a serial I2C and SPI interface. The driver currently
24 I2C bus address of the display.
26 display-height-chars:
27 description: Height of the display, in character cells.
32 display-width-chars:
33 description: Width of the display, in character cells.
41 - display-height-chars
42 - display-width-chars
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Dhit,hd44780.yaml14 LCDs that can display one or more lines of text. It exposes an M6800 bus
54 display-height-chars:
55 description: Height of the display, in character cells,
60 display-width-chars:
61 description: Width of the display, in character cells.
69 display-width-chars for displays with more than 2 lines).
79 - display-height-chars
80 - display-width-chars
97 display-height-chars = <2>;
98 display-width-chars = <16>;
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/Documentation/devicetree/bindings/display/sprd/
Dsprd,display-subsystem.yaml4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
14 DPU devices or other display interface nodes that comprise the
17 Unisoc's display pipeline have several components as below description,
18 multi display controllers and corresponding physical interfaces.
19 For different display scenarios, dpu0 and dpu1 maybe binding to different
23 dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
24 dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;
44 const: sprd,display-subsystem
51 Should contain a list of phandles pointing to display interface port
62 display-subsystem {
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/Documentation/userspace-api/media/v4l/
Dext-ctrls-colorimetry.rst49 The mastering display defines the color volume (the color primaries,
50 white point and luminance range) of a display considered to be the
51 mastering display for the current video content.
65 primary component c of the mastering display in increments of 0.00002.
66 For describing the mastering display that uses Red, Green and Blue
73 primary component c of the mastering display in increments of 0.00002.
74 For describing the mastering display that uses Red, Green and Blue
81 point of the mastering display in increments of 0.00002.
85 point of the mastering display in increments of 0.00002.
88 - Specifies the nominal maximum display luminance of the mastering
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/Documentation/devicetree/bindings/display/msm/
Dqcom,sm6115-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
7 title: Qualcomm Display DPU on SM6115
12 $ref: /schemas/display/msm/dpu-common.yaml#
30 - description: Display AXI
31 - description: Display AHB
32 - description: Display core
33 - description: Display lut
34 - description: Display rotator
35 - description: Display vsync
61 display-controller@5e01000 {
Dqcom,sc7180-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
7 title: Qualcomm Display DPU on SC7180
12 $ref: /schemas/display/msm/dpu-common.yaml#
35 - description: Display hf axi clock
36 - description: Display ahb clock
37 - description: Display rotator clock
38 - description: Display lut clock
39 - description: Display core clock
40 - description: Display vsync clock
41 - description: Display core throttle clock
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Dqcom,sc7280-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
7 title: Qualcomm Display DPU on SC7280
12 $ref: /schemas/display/msm/dpu-common.yaml#
30 - description: Display hf axi clock
31 - description: Display sf axi clock
32 - description: Display ahb clock
33 - description: Display lut clock
34 - description: Display core clock
35 - description: Display vsync clock
61 display-controller@ae01000 {
Dqcom,sc8280xp-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
7 title: Qualcomm SC8280XP Display Processing Unit
13 Device tree bindings for SC8280XP Display Processing Unit.
15 $ref: /schemas/display/msm/dpu-common.yaml#
33 - description: Display hf axi clock
34 - description: Display sf axi clock
35 - description: Display ahb clock
36 - description: Display lut clock
37 - description: Display core clock
38 - description: Display vsync clock
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Dqcom,qcm2290-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
7 title: Qualcomm Display DPU on QCM2290
12 $ref: /schemas/display/msm/dpu-common.yaml#
30 - description: Display AXI clock from gcc
31 - description: Display AHB clock from dispcc
32 - description: Display core clock from dispcc
33 - description: Display lut clock from dispcc
34 - description: Display vsync clock from dispcc
59 display-controller@5e01000 {
Dqcom,sdm845-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
7 title: Qualcomm Display DPU on SDM845
12 $ref: /schemas/display/msm/dpu-common.yaml#
30 - description: Display GCC bus clock
31 - description: Display ahb clock
32 - description: Display axi clock
33 - description: Display core clock
34 - description: Display vsync clock
59 display-controller@ae01000 {
Dqcom,msm8998-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
7 title: Qualcomm Display DPU on MSM8998
12 $ref: /schemas/display/msm/dpu-common.yaml#
34 - description: Display ahb clock
35 - description: Display axi clock
36 - description: Display mem-noc clock
37 - description: Display core clock
38 - description: Display vsync clock
62 display-controller@c901000 {
Dqcom,sm8550-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
7 title: Qualcomm SM8550 Display DPU
12 $ref: /schemas/display/msm/dpu-common.yaml#
30 - description: Display AHB
31 - description: Display hf axi
32 - description: Display MDSS ahb
33 - description: Display lut
34 - description: Display core
35 - description: Display vsync
62 display-controller@ae01000 {
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra186-dc.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
7 title: NVIDIA Tegra186 (and later) Display Controller
15 pattern: "^display@[0-9a-f]+$"
30 - description: display controller pixel clock
38 - description: display controller reset
52 display controller; see ../interconnect/interconnect.txt
61 description: A list of phandles of outputs that this display
66 description: The number of the display controller head. This
85 # see nvidia,tegra186-display.yaml for examples
Dnvidia,tegra186-display.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
7 title: NVIDIA Tegra186 (and later) Display Hub
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
44 - description: display hub reset
69 "^display@[0-9a-f]+$":
77 const: nvidia,tegra186-display
82 - description: display core clock
83 - description: display stream compression clock
[all …]
/Documentation/devicetree/bindings/display/panel/
Ddisplay-timings.yaml4 $id: http://devicetree.org/schemas/display/panel/display-timings.yaml#
7 title: display timings
15 A display panel may be able to handle several display timings,
17 The display-timings node makes it possible to specify the timings
18 and to specify the timing that is native for the display.
22 const: display-timings
27 The default display timing is the one specified as native-mode.
46 display-timings {
/Documentation/devicetree/bindings/display/rockchip/
Drockchip-drm.yaml4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-drm.yaml#
15 vop devices or other display interface nodes that comprise the
20 const: rockchip,display-subsystem
27 Should contain a list of phandles pointing to display interface port
29 Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml
39 display-subsystem {
40 compatible = "rockchip,display-subsystem";
/Documentation/devicetree/bindings/display/imx/
Dldb.txt1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
14 multiplexer in the front to select any of the four IPU display
20 the display interface selector clocks, as described in
48 or a display-timings node that describes the video timings for the connected
49 LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
62 display-timings are used instead.
64 Optional properties (required if display-timings are used):
66 - display-timings : A node that describes the display timings as defined in
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