| /Documentation/devicetree/bindings/pinctrl/ |
| D | cirrus,lochnagar.yaml | 72 enum: [ codec-aif1, codec-aif2, codec-aif3, dsp-aif1,
73 dsp-aif2, psia1, psia2, gf-aif1, gf-aif2, gf-aif3,
84 codec-gpio7, codec-gpio8, dsp-gpio1, dsp-gpio2,
85 dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6,
90 codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk,
91 dsp-aif1-rxdat, dsp-aif1-lrclk, dsp-aif1-txdat,
92 dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk,
93 dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk,
100 gf-aif2-lrclk, gf-aif2-txdat, dsp-uart1-rx,
101 dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx,
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| /Documentation/devicetree/bindings/dsp/ |
| D | mediatek,mt8186-dsp.yaml | 4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml#
7 title: MediaTek mt8186 DSP core
13 MediaTek mt8186 SoC contains a DSP core used for
19 - mediatek,mt8186-dsp
20 - mediatek,mt8188-dsp
24 - description: Address and size of the DSP config registers
25 - description: Address and size of the DSP SRAM
26 - description: Address and size of the DSP secure registers
27 - description: Address and size of the DSP bus registers
38 - description: mux for audio dsp clock
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| D | mediatek,mt8195-dsp.yaml | 4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
7 title: Mediatek mt8195 DSP core
13 Some boards from mt8195 contain a DSP core used for
18 const: mediatek,mt8195-dsp
22 - description: Address and size of the DSP Cfg registers
23 - description: Address and size of the DSP SRAM
32 - description: mux for audio dsp clock
34 - description: mux for audio dsp local bus
35 - description: default audio dsp local bus clock source
36 - description: clock gate for audio dsp clock
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| D | fsl,dsp.yaml | 4 $id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#
7 title: NXP i.MX8 DSP core
14 Some boards from i.MX8 family contain a DSP core used for
20 - fsl,imx8qxp-dsp
21 - fsl,imx8qm-dsp
22 - fsl,imx8mp-dsp
23 - fsl,imx8ulp-dsp
72 used by DSP (see bindings/reserved-memory/reserved-memory.txt)
80 fsl,dsp-ctrl:
101 - fsl,imx8qxp-dsp
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,davinci-rproc.txt | 1 TI Davinci DSP devices
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
13 controller, a dedicated local power/sleep controller etc. The DSP processor
14 core used in Davinci SoCs is usually a C674x DSP CPU.
16 DSP Device Node:
18 Each DSP Core sub-system is represented as a single DT node.
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
38 interrupts from the DSP. The value should follow the
52 /* DSP Reserved Memory node */
58 dsp_memory_region: dsp-memory@c3000000 {
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| D | ti,keystone-rproc.txt | 1 TI Keystone DSP devices
4 The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
10 a dedicated local power/sleep controller etc. The DSP processor core in
13 DSP Device Node:
15 Each DSP Core sub-system is represented as a single DT node, and should also
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
29 "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
42 State Control node, and the register offset of the DSP
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| D | ti,k3-dsp-rproc.yaml | 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
7 title: TI K3 DSP devices
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
19 controller, a dedicated local power/sleep controller etc. The DSP processor
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
34 - ti,am62a-c7xv-dsp
35 - ti,j721e-c66-dsp
36 - ti,j721e-c71-dsp
37 - ti,j721s2-c71-dsp
39 Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs
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| D | ti,omap-remoteproc.yaml | 21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
42 - ti,omap4-dsp
43 - ti,omap5-dsp
44 - ti,dra7-dsp
108 'reg-names'. These are mandatory for all DSP and IPU
132 This property is required for all the DSP instances on OMAP4, OMAP5
177 - ti,dra7-dsp
225 //Example 1: OMAP4 DSP
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-dsp-keystone.txt | 1 Keystone 2 DSP GPIO controller bindings
3 HOST OS userland running on ARM can send interrupts to DSP cores using
4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
7 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
10 Keystone 2 DSP GPIO controller has specific features:
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
17 - compatible: should be "ti,keystone-dsp-gpio"
29 compatible = "ti,keystone-dsp-gpio";
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | dsp.txt | 1 * TI - DSP (Digital Signal Processor)
3 TI DSP included in OMAP SoC
7 - ti,hwmods: "dsp"
11 dsp {
13 ti,hwmods = "dsp";
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| /Documentation/hwmon/ |
| D | lochnagar.rst | 33 in1_input Measured voltage for 1V8 DSP (milliVolts)
34 in1_label "1V8 DSP"
35 curr2_input Measured current for 1V8 DSP (milliAmps)
36 curr2_label "1V8 DSP"
37 power2_average Measured average power for 1V8 DSP (microWatts)
39 power2_label "1V8 DSP"
47 in3_input Measured voltage for VDDCORE DSP (milliVolts)
48 in3_label "VDDCORE DSP"
49 curr4_input Measured current for VDDCORE DSP (milliAmps)
50 curr4_label "VDDCORE DSP"
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| /Documentation/devicetree/bindings/iommu/ |
| D | ti,omap-iommu.txt | 7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
27 is required for DSP IOMMU instances on DRA7xx SoCs. The
28 instance number should be 0 for DSP MDMA MMUs and 1 for
29 DSP EDMA MMUs.
44 compatible = "ti,dra7-dsp-iommu";
53 compatible = "ti,dra7-dsp-iommu";
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| /Documentation/sound/soc/ |
| D | dpcm.rst | 10 digital audio to I2S DAI0, I2S DAI1 or PDM DAI2. This is useful for on SoC DSP
15 graph representing the DSP internal audio paths and uses the mixer settings to
22 Phone Audio System with SoC based DSP
29 | Front End PCMs | SoC DSP | Back End DAIs | Audio devices |
35 * DSP *
47 modem. This sound card exposes 4 DSP front end (FE) ALSA PCM devices and
66 * DSP *
83 * DSP *
130 | Front End PCMs | SoC DSP | Back End DAIs | Audio devices |
136 * DSP *
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| D | platform.rst | 6 drivers and DSP drivers. The platform drivers only target the SoC CPU and must
68 SoC DSP Drivers
71 Each SoC DSP driver usually supplies the following features :-
75 3. DMA IO to/from DSP buffers (if applicable)
76 4. Definition of DSP front end (FE) PCM devices.
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| D | codec-to-codec.rst | 64 .name = "CPU-DSP",
65 .stream_name = "CPU-DSP",
76 .name = "DSP-CODEC",
77 .stream_name = "DSP-CODEC",
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| /Documentation/devicetree/bindings/sound/ |
| D | tas5805m.yaml | 13 The TAS5805M is a class D audio amplifier with a built-in DSP.
33 ti,dsp-config-name:
35 The name of the DSP configuration that should be loaded for this
52 ti,dsp-config-name = "mono_pbtl_48khz";
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| D | qcom,q6dsp-lpass-clocks.yaml | 7 title: Qualcomm DSP LPASS Clock Controller
13 This binding describes the Qualcomm DSP Clock Controller
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| /Documentation/devicetree/bindings/misc/ |
| D | qcom,fastrpc.yaml | 15 invocations across DSP and APPS boundaries. This enables developers
16 to offload tasks to the DSP and free up the application processor for
41 - const: fastrpcglink-apps-dsp
53 - const: fastrpcsmd-apps-dsp
71 Each subnode of the Fastrpc represents compute context banks available on the dsp.
120 qcom,glink-channels = "fastrpcglink-apps-dsp";
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| /Documentation/sound/cards/ |
| D | emu-mixer.rst | 2 E-MU Digital Audio System mixer / default DSP code
65 and the DSP microcontroller can operate with the resulting sum.
102 samples for 5.1 playback. The result samples are forwarded to the DSP 0 & 1
109 samples for 5.1 playback. The result samples are forwarded to the DSP 2 & 3
116 samples for 7.1 playback. The result samples are forwarded to the DSP 6 & 7
123 are forwarded to the DSP 4 playback channel.
129 are forwarded to the DSP 5 playback channel.
158 The result samples are forwarded to the DSP 0 & 1 playback channels.
163 The result samples are forwarded to the DSP 2 & 3 playback channels.
168 The result samples are forwarded to the DSP 6 & 7 playback channels.
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| /Documentation/devicetree/bindings/dma/ |
| D | stericsson,dma40.yaml | 46 24: Multimedia DSP SXA0
47 25: Multimedia DSP SXA1
48 26: Multimedia DSP SXA2
49 27: Multimedia DSP SXA3
66 44: Multimedia DSP SXA4
67 45: Multimedia DSP SXA5
68 46: SLIMbus channel 8 or Multimedia DSP SXA6
69 47: SLIMbus channel 9 or Multimedia DSP SXA7
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| /Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | gamecube.txt | 45 1.c) The Digital Signal Processor (DSP) node
52 - compatible : should be "nintendo,flipper-dsp"
53 - reg : should contain the DSP registers location and length
54 - interrupts : should contain the DSP interrupt
60 The ARAM node must be placed under the DSP node.
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| D | wii.txt | 56 1.c) The Digital Signal Processor (DSP) node
63 - compatible : should be "nintendo,hollywood-dsp","nintendo,flipper-dsp"
64 - reg : should contain the DSP registers location and length
65 - interrupts : should contain the DSP interrupt
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| /Documentation/sound/designs/ |
| D | compress-offload.rst | 17 In recent years, audio digital signal processors (DSP) were integrated
68 streaming compressed data to a DSP, with the assumption that the
75 DSP, eg. Android HAL or PulseAudio sinks. By construction, regular
95 is transmitted to the audio DSP. DMA transfers from main memory to an
132 This routines returns the actual settings used by the DSP. Changes to
140 refilled or the delay due to decoding/encoding/io on the DSP.
216 So we need to pass this to DSP. This metadata is extracted from ID3/MP4 headers
218 interface to pass this information to the DSP. Also DSP and userspace needs to
229 This routine tells DSP that metadata and write operation sent after this would
233 This is called when end of file is reached. The userspace can inform DSP that
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| /Documentation/devicetree/bindings/mfd/ |
| D | stericsson,db8500-prcmu.yaml | 123 description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
124 voltage regulator. This is the voltage for the accelerator DSP
131 description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
138 description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
145 description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
146 voltage regulator. This is the voltage for the accelerator DSP
153 description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
160 description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,keystone-irq.txt | 3 On Keystone SOCs, DSP cores can send interrupts to ARM
5 The IRQ handler running on HOST OS can identify DSP signal source by
|