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/Documentation/admin-guide/perf/ |
D | meson-ddr-pmu.rst | 26 + arm - from CPU 27 + vpu_read1 - from OSD + VPP read 28 + gpu - from 3D GPU 29 + pcie - from PCIe controller 30 + hdcp - from HDCP controller 31 + hevc_front - from HEVC codec front end 32 + usb3_0 - from USB3.0 controller 33 + hevc_back - from HEVC codec back end 34 + h265enc - from HEVC encoder 35 + vpu_read2 - from DI read [all …]
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/Documentation/hwmon/ |
D | ucd9200.rst | 29 [From datasheets] UCD9220, UCD9222, UCD9224, UCD9240, UCD9244, UCD9246, and 62 in1_input Measured voltage. From READ_VIN register. 63 in1_min Minimum Voltage. From VIN_UV_WARN_LIMIT register. 64 in1_max Maximum voltage. From VIN_OV_WARN_LIMIT register. 66 in1_crit Critical maximum voltage. From VIN_OV_FAULT_LIMIT 68 in1_min_alarm Voltage low alarm. From VIN_UV_WARNING status. 69 in1_max_alarm Voltage high alarm. From VIN_OV_WARNING status. 70 in1_lcrit_alarm Voltage critical low alarm. From VIN_UV_FAULT status. 71 in1_crit_alarm Voltage critical high alarm. From VIN_OV_FAULT status. 74 in[2-5]_input Measured voltage. From READ_VOUT register. [all …]
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D | pmbus.rst | 185 supported, and determines available sensors from this information. 194 inX_input Measured voltage. From READ_VIN or READ_VOUT register. 196 From VIN_UV_WARN_LIMIT or VOUT_UV_WARN_LIMIT register. 198 From VIN_OV_WARN_LIMIT or VOUT_OV_WARN_LIMIT register. 200 From VIN_UV_FAULT_LIMIT or VOUT_UV_FAULT_LIMIT register. 202 From VIN_OV_FAULT_LIMIT or VOUT_OV_FAULT_LIMIT register. 203 inX_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status. 204 inX_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status. 206 From VOLTAGE_UV_FAULT status. 208 From VOLTAGE_OV_FAULT status. [all …]
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D | max8688.rst | 49 in1_input Measured voltage. From READ_VOUT register. 50 in1_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register. 51 in1_max Maximum voltage. From VOUT_OV_WARN_LIMIT register. 53 in1_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT 55 in1_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status. 56 in1_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status. 57 in1_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT 59 in1_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT 65 curr1_input Measured current. From READ_IOUT register. 66 curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register. [all …]
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D | f71882fg.rst | 10 Addresses scanned: none, address read from Super I/O config space 18 Addresses scanned: none, address read from Super I/O config space 26 Addresses scanned: none, address read from Super I/O config space 28 Datasheet: Available from the Fintek website 34 Addresses scanned: none, address read from Super I/O config space 36 Datasheet: Available from the Fintek website 42 Addresses scanned: none, address read from Super I/O config space 44 Datasheet: Available from the Fintek website 50 Addresses scanned: none, address read from Super I/O config space 58 Addresses scanned: none, address read from Super I/O config space [all …]
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D | tps40422.rst | 48 in[1-2]_input Measured voltage. From READ_VOUT register. 51 curr[1-2]_input Measured current. From READ_IOUT register. 53 curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register. 54 curr1_crit Critical maximum current. From IOUT_OC_FAULT_LIMIT 56 curr1_max_alarm Current high alarm. From IOUT_OC_WARN_LIMIT status. 57 curr1_crit_alarm Current critical high alarm. From IOUT_OC_FAULT status. 58 curr2_alarm Current high alarm. From IOUT_OC_WARNING status. 60 temp1_input Measured temperature. From READ_TEMPERATURE_2 register 62 temp1_max Maximum temperature. From OT_WARN_LIMIT register. 63 temp1_crit Critical high temperature. From OT_FAULT_LIMIT register. [all …]
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D | max16064.rst | 49 in[1-4]_input Measured voltage. From READ_VOUT register. 50 in[1-4]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register. 51 in[1-4]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register. 53 in[1-4]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT 55 in[1-4]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status. 56 in[1-4]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status. 57 in[1-4]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT 59 in[1-4]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT 64 temp1_input Measured temperature. From READ_TEMPERATURE_1 register. 65 temp1_max Maximum temperature. From OT_WARN_LIMIT register. [all …]
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D | ucd9000.rst | 28 From datasheets: 94 in[1-12]_input Measured voltage. From READ_VOUT register. 95 in[1-12]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register. 96 in[1-12]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register. 98 in[1-12]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT 100 in[1-12]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status. 101 in[1-12]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status. 102 in[1-12]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT 104 in[1-12]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT 108 curr[1-12]_input Measured current. From READ_IOUT register. [all …]
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D | nct6775.rst | 15 Addresses scanned: ISA address retrieved from Super I/O registers 17 Datasheet: Available from the Nuvoton web site 23 Addresses scanned: ISA address retrieved from Super I/O registers 25 Datasheet: Available from Nuvoton upon request 31 Addresses scanned: ISA address retrieved from Super I/O registers 33 Datasheet: Available from Nuvoton upon request 39 Addresses scanned: ISA address retrieved from Super I/O registers 41 Datasheet: Available from Nuvoton upon request 47 Addresses scanned: ISA address retrieved from Super I/O registers 49 Datasheet: Available from Nuvoton upon request [all …]
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/Documentation/devicetree/bindings/clock/ |
D | samsung,exynos850-clock.yaml | 24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. 88 - description: CMU_APM bus clock (from CMU_TOP) 106 - description: AUD clock (from CMU_TOP) 124 - description: CMU_CMGP bus clock (from CMU_APM) 142 - description: CMU_CORE bus clock (from CMU_TOP) 143 - description: CCI clock (from CMU_TOP) 144 - description: eMMC clock (from CMU_TOP) 145 - description: SSS clock (from CMU_TOP) 166 - description: DPU clock (from CMU_TOP) 184 - description: G3D clock (from CMU_TOP) [all …]
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D | samsung,exynos7885-clock.yaml | 24 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. 81 - description: CMU_CORE bus clock (from CMU_TOP) 82 - description: CCI clock (from CMU_TOP) 83 - description: G3D clock (from CMU_TOP) 103 - description: CMU_FSYS bus clock (from CMU_TOP) 104 - description: MMC_CARD clock (from CMU_TOP) 105 - description: MMC_EMBD clock (from CMU_TOP) 106 - description: MMC_SDIO clock (from CMU_TOP) 107 - description: USB30DRD clock (from CMU_TOP) 129 - description: CMU_PERI bus clock (from CMU_TOP) [all …]
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D | qcom,sm8450-dispcc.yaml | 30 - description: Byte clock from DSI PHY0 31 - description: Pixel clock from DSI PHY0 32 - description: Byte clock from DSI PHY1 33 - description: Pixel clock from DSI PHY1 34 - description: Link clock from DP PHY0 35 - description: VCO DIV clock from DP PHY0 36 - description: Link clock from DP PHY1 37 - description: VCO DIV clock from DP PHY1 38 - description: Link clock from DP PHY2 39 - description: VCO DIV clock from DP PHY2 [all …]
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D | qcom,sm8550-dispcc.yaml | 30 - description: Byte clock from DSI PHY0 31 - description: Pixel clock from DSI PHY0 32 - description: Byte clock from DSI PHY1 33 - description: Pixel clock from DSI PHY1 34 - description: Link clock from DP PHY0 35 - description: VCO DIV clock from DP PHY0 36 - description: Link clock from DP PHY1 37 - description: VCO DIV clock from DP PHY1 38 - description: Link clock from DP PHY2 39 - description: VCO DIV clock from DP PHY2 [all …]
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D | cirrus,lochnagar.yaml | 48 - ln-cdc-clkout # Output clock from CODEC card. 49 - ln-dsp-clkout # Output clock from DSP card. 50 - ln-gf-mclk1 # Optional input clock from host system. 51 - ln-gf-mclk2 # Optional input clock from host system. 52 - ln-gf-mclk3 # Optional input clock from host system. 53 - ln-gf-mclk4 # Optional input clock from host system. 54 - ln-psia1-mclk # Optional input clock from external connector. 55 - ln-psia2-mclk # Optional input clock from external connector. 56 - ln-spdif-mclk # Optional input clock from SPDIF. 57 - ln-spdif-clkout # Optional input clock from SPDIF. [all …]
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D | tesla,fsd-clock.yaml | 16 The root clock comes from external OSC clock (24 MHz). 71 - description: IMEM TCU clock (from CMU_CMU) 72 - description: IMEM bus clock (from CMU_CMU) 73 - description: IMEM DMA clock (from CMU_CMU) 91 - description: Shared0 PLL div4 clock (from CMU_CMU) 92 - description: PERIC shared1 div36 clock (from CMU_CMU) 93 - description: PERIC shared0 div3 TBU clock (from CMU_CMU) 94 - description: PERIC shared0 div20 clock (from CMU_CMU) 95 - description: PERIC shared1 div4 DMAclock (from CMU_CMU) 115 - description: Shared0 PLL div6 clock (from CMU_CMU) [all …]
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D | samsung,exynosautov9-clock.yaml | 25 derived from CMU_TOP. 87 - description: CMU_BUSMC bus clock (from CMU_TOP) 105 - description: CMU_CORE bus clock (from CMU_TOP) 123 - description: CMU_FSYS0 bus clock (from CMU_TOP) 124 - description: CMU_FSYS0 pcie clock (from CMU_TOP) 143 - description: CMU_FSYS1 bus clock (from CMU_TOP) 144 - description: CMU_FSYS1 mmc card clock (from CMU_TOP) 145 - description: CMU_FSYS1 usb clock (from CMU_TOP) 165 - description: CMU_FSYS2 bus clock (from CMU_TOP) 166 - description: UFS clock (from CMU_TOP) [all …]
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D | qcom,sdm845-dispcc.yaml | 28 - description: GPLL0 source from GCC 29 - description: GPLL0 div source from GCC 30 - description: Byte clock from DSI PHY0 31 - description: Pixel clock from DSI PHY0 32 - description: Byte clock from DSI PHY1 33 - description: Pixel clock from DSI PHY1 34 - description: Link clock from DP PHY 35 - description: VCO DIV clock from DP PHY
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D | qcom,sc7280-dispcc.yaml | 25 - description: GPLL0 source from GCC 26 - description: Byte clock from DSI PHY 27 - description: Pixel clock from DSI PHY 28 - description: Link clock from DP PHY 29 - description: VCO DIV clock from DP PHY 30 - description: Link clock from EDP PHY 31 - description: VCO DIV clock from EDP PHY
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/Documentation/admin-guide/ |
D | numastat.rst | 10 are able to allocate memory from nodes they prefer. If they succeed, numa_hit 17 incremented on allocation from a node by CPU on the same node. other_node is 19 from a CPU from a different node. Note there is no counter analogical to 25 numa_hit A process wanted to allocate memory from this node, 28 numa_miss A process wanted to allocate memory from another node, 29 but ended up with memory from this node. 32 but ended up with memory from another node. 35 and got memory from this node. 38 and got memory from this node. 40 interleave_hit Interleaving wanted to allocate from this node [all …]
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/Documentation/devicetree/bindings/display/exynos/ |
D | exynos_dp.txt | 15 For the Panel initialization, we read data from dp-controller node. 25 from common clock binding: handle to dp clock. 27 from common clock binding: Shall be "dp". 29 from general PHY binding: the phandle for the PHY device. 31 from general PHY binding: Should be "dp". 60 -interlaced: deprecated prop that can parsed from drm_display_mode. 61 -vsync-active-high: deprecated prop that can parsed from drm_display_mode. 62 -hsync-active-high: deprecated prop that can parsed from drm_display_mode. 63 -samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode. 64 -samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode. [all …]
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/Documentation/scsi/ |
D | ChangeLog.lpfc | 5 Changes from 20050323 to 20050413 11 * Merged patch from Christoph Hellwig <hch@lst.de>: split helpers 24 only be called from lpfc_sli_submit_iocb. Also make 47 Changes from 20050308 to 20050323 50 * Changed a few lines from patch submitted by Christoph Hellwig 53 * Merged patch from Christoph Hellwig (3/19): some misc patches 64 - don't call dma_sync function on allocations from 66 * Merged patch from Christoph Hellwig (3/19) - nlp_failMask isn't 73 * Merged patch from Christoph Hellwig (03/19) - fix initialization 74 order - scsi_add_host must happen last from scsi POV. Also some [all …]
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/Documentation/ABI/testing/ |
D | sysfs-bus-coresight-devices-etb10 | 5 Description: (RW) Add/remove a sink from a trace path. There can be multiple 20 value stored in this register+1 (from ARM ETB-TRM). 27 2. The value is read directly from HW register RDP, 0x004. 34 is read directly from HW register STS, 0x00C. 41 that is used to read entries from the Trace RAM over the APB 42 interface. The value is read directly from HW register RRP, 50 that is used to sets the write pointer to write entries from 52 from HW register RWP, 0x018. 59 read directly from HW register TRG, 0x01C. 66 is read directly from HW register CTL, 0x020. [all …]
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D | sysfs-bus-coresight-devices-tmc | 15 The value is read directly from HW register RSZ, 0x004. 22 is read directly from HW register STS, 0x00C. 29 that is used to read entries from the Trace RAM over the APB 30 interface. The value is read directly from HW register RRP, 38 that is used to sets the write pointer to write entries from 40 from HW register RWP, 0x018. 47 read directly from HW register TRG, 0x01C. 54 is read directly from HW register CTL, 0x020. 61 register. The value is read directly from HW register FFSR, 69 register. The value is read directly from HW register FFCR, [all …]
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D | sysfs-devices-power | 15 from sleep states, such as the memory sleep state (suspend to 20 used to activate the system from a sleep state. Such devices 33 be enabled to wake up the system from sleep states. 46 + "on\n" to prevent the device from being power managed; 51 from power managing the device at run time. Doing that while 87 the system from sleep states, this attribute is not present. 88 If the device is not enabled to wake up the system from sleep 99 system from sleep states, this attribute is not present. If 100 the device is not enabled to wake up the system from sleep 111 is not capable to wake up the system from sleep states, this [all …]
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/Documentation/driver-api/ |
D | device_link.rst | 55 or the device link needs to be added from a function which is guaranteed 56 not to run in parallel to a suspend/resume transition, such as from a 60 represents a driver presence dependency, yet is added from the consumer's 65 non-presence. [Note that it is valid to create a link from the consumer's 87 link is added from the consumer's ``->probe`` callback: ``DL_FLAG_RPM_ACTIVE`` 88 can be specified to runtime resume the supplier and prevent it from suspending 93 Similarly, when the device link is added from supplier's ``->probe`` callback, 160 runtime PM integration is added from the busmaster device (consumer) 172 and an NHI device to manage the PCIe switch. On resume from system sleep, 177 device links from the hotplug ports (consumers) to the NHI device [all …]
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