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/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
[all …]
Dmti,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
[all …]
Drenesas,rza1-irqc.yaml14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Darm,gic-v3.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
[all …]
Dfsl,ls-extirq.yaml50 description: Specifies the mapping from external interrupts to GIC interrupts.
103 #include <dt-bindings/interrupt-controller/arm-gic.h>
111 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
112 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
113 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
114 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
115 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
116 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
Dmarvell,gicp.txt4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
Dti,omap4-wugen-mpu4 routes interrupts to the GIC, and also serves as a wakeup source. It
18 - Because this HW ultimately routes interrupts to the GIC, the
19 interrupt specifier must be that of the GIC.
30 interrupt-parent = <&gic>;
Dmarvell,icu.txt6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
39 - msi-parent: Should point to the GICP controller, the GIC extension
95 The 3rd cell was the type of the interrupt. See arm,gic.txt for
Dmstar,mst-intc.yaml14 interrupt controllers that routes interrupts to the GIC.
28 Use the same format as specified by GIC in arm,gic.yaml.
60 interrupt-parent = <&gic>;
Dqcom,mpm.yaml17 one of these interrupts occur and replays it to GIC interrupt controller
18 after GIC becomes operational.
58 A set of MPM pin numbers and the corresponding GIC SPIs.
63 - description: GIC SPI number for the MPM pin
82 #include <dt-bindings/interrupt-controller/arm-gic.h>
Dmediatek,sysirq.txt3 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
30 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
41 interrupt-parent = <&gic>;
Dmarvell,odmi-controller.txt23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
26 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
27 for details about the GIC Device Tree binding.
Dnvidia,tegra20-ictlr.txt4 interrupts to the GIC, and also serves as a wakeup source. It is also
25 - Because this HW ultimately routes interrupts to the GIC, the
26 interrupt specifier must be that of the GIC.
Dbrcm,bcm7120-l2-intc.yaml14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
36 0 -----[ MUX ] ------------|==========> GIC interrupt 75
39 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
42 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
48 7 ---------------------|---|===========> GIC interrupt 66
54 |===========> GIC interrupt 64
Dqcom,pdc.yaml17 well detect interrupts when the GIC is non-operational.
19 GIC is parent interrupt controller at the highest level. Platform interrupt
23 with the GIC interrupt. See example below.
63 - description: GIC hwirq number for the PDC port
Dmicrochip,sama7g5-eic.yaml34 Contains the GIC SPI IRQs mapped to the external interrupt lines. They
59 #include <dt-bindings/interrupt-controller/arm-gic.h>
64 interrupt-parent = <&gic>;
/Documentation/devicetree/bindings/bus/
Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/devicetree/bindings/pci/
Dhisilicon,kirin-pcie.yaml67 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
95 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
96 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
97 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
126 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
127 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
128 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
129 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
Dmediatek,mt7621-pcie.yaml77 #include <dt-bindings/interrupt-controller/mips-gic.h>
95 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
96 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
97 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
122 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
137 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
Dtoshiba,visconti-pcie.yaml73 #include <dt-bindings/interrupt-controller/arm-gic.h>
102 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
103 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
104 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
105 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
Dxgene-pci.txt43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
46 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
Dcdns,cdns-pcie-host.yaml62 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>,
63 <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>,
64 <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>,
65 <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
Dlayerscape-pcie-gen4.txt48 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
49 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
50 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
51 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.txt38 For GICv3 and GIC ITS bindings, see:
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
127 - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
131 (icid-base,gic-its,msi-base,length).
134 associated with the listed GIC ITS, with the msi-specifier
158 gic: interrupt-controller@6000000 {
159 compatible = "arm,gic-v3";
162 its: gic-its@6020000 {
163 compatible = "arm,gic-v3-its";
/Documentation/devicetree/bindings/timer/
Dsamsung,exynos4210-mct.yaml160 #include <dt-bindings/interrupt-controller/arm-gic.h>
180 #include <dt-bindings/interrupt-controller/arm-gic.h>
188 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
189 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
192 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
193 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
201 #include <dt-bindings/interrupt-controller/arm-gic.h>
221 #include <dt-bindings/interrupt-controller/arm-gic.h>

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