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/Documentation/devicetree/bindings/gpio/
D8xxx_gpio.txt1 GPIO controllers on MPC8xxx SoCs
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
8 See bindings/gpio/gpio.txt for details of how to specify GPIO
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
[all …]
Dgpio-mxs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MXS GPIO controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <Anson.Huang@nxp.com>
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
17 GPIO ports share the same IO space with PIN controller, the GPIO node
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Dintel,ixp4xx-gpio.txt1 Intel IXP4xx XScale Networking Processors GPIO
3 This GPIO controller is found in the Intel IXP4xx processors.
4 It supports 16 GPIO lines.
6 The interrupt portions of the GPIO controller is hierarchical:
7 the synchronous edge detector is part of the GPIO block, but the
9 main IXP4xx interrupt controller which has a 1:1 mapping for
10 the first 12 GPIO lines to 12 system interrupts.
12 The remaining 4 GPIO lines can not be used for receiving
15 The interrupt parent of this GPIO controller must be the
16 IXP4xx interrupt controller.
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Dgpio-ep9301.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-ep9301.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EP93xx GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
12 - Nikita Shubin <nikita.shubin@maquefel.me>
17 - const: cirrus,ep9301-gpio
18 - items:
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Drealtek,otto-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek Otto GPIO controller
10 - Sander Vanheule <sander@svanheule.net>
11 - Bert Vermeulen <bert@biot.com>
14 Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists
15 of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.
17 interrupt controller, if provided.
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Dnxp,lpc1850-gpio.txt1 NXP LPC18xx/43xx GPIO controller Device Tree Bindings
2 -----------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-gpio"
6 - reg : List of addresses and lengths of the GPIO controller
8 - reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
9 "gpio-gpoup1-ic"
10 - clocks : Phandle and clock specifier pair for GPIO controller
11 - resets : Phandle and reset specifier pair for GPIO controller
12 - gpio-controller : Marks the device node as a GPIO controller
13 - #gpio-cells : Should be two:
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Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
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Dbrcm,kona-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,kona-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family GPIO controller
10 The Broadcom GPIO Controller IP can be configured prior to synthesis to
12 GPIO controller only supports edge, not level, triggering of interrupts.
15 - Ray Jui <rjui@broadcom.com>
20 - enum:
21 - brcm,bcm11351-gpio
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Dcdns,gpio.txt1 Cadence GPIO controller bindings
4 - compatible: should be "cdns,gpio-r1p02".
5 - reg: the register base address and size.
6 - #gpio-cells: should be 2.
7 * first cell is the GPIO number.
8 * second cell specifies the GPIO flags, as defined in
9 <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
11 - gpio-controller: marks the device as a GPIO controller.
12 - clocks: should contain one entry referencing the peripheral clock driving
13 the GPIO controller.
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Dgpio-aspeed.txt1 Aspeed GPIO controller Device Tree Bindings
2 -------------------------------------------
5 - compatible : Either "aspeed,ast2400-gpio", "aspeed,ast2500-gpio",
6 or "aspeed,ast2600-gpio".
8 - #gpio-cells : Should be two
9 - First cell is the GPIO line number
10 - Second cell is used to specify optional
13 - reg : Address and length of the register set for the device
14 - gpio-controller : Marks the device node as a GPIO controller.
15 - interrupts : Interrupt specifier (see interrupt bindings for
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Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
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Dmediatek,mt7621-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/mediatek,mt7621-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek MT7621 SoC GPIO controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
15 We load one GPIO controller instance per bank. Also the GPIO controller can receive
21 pattern: "^gpio@[0-9a-f]+$"
24 const: mediatek,mt7621-gpio
29 "#gpio-cells":
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Dnvidia,tegra186-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
20 The Tegra186 GPIO controller allows software to set the IO direction of,
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Dgpio-xgene.txt1 APM X-Gene SoC GPIO controller bindings
3 This is a gpio controller that is part of the flash controller.
4 This gpio controller controls a total of 48 gpios.
7 - compatible: "apm,xgene-gpio" for X-Gene GPIO controller
8 - reg: Physical base address and size of the controller's registers
9 - #gpio-cells: Should be two.
10 - first cell is the pin number
11 - second cell is used to specify the gpio polarity:
14 - gpio-controller: Marks the device node as a GPIO controller.
18 compatible = "apm,xgene-gpio";
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Dgpio-altera.txt1 Altera GPIO controller bindings
4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
7 - #gpio-cells : Should be 2
8 - The first cell is the gpio offset number.
9 - The second cell is reserved and is currently unused.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 - #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
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Dabilis,tb10x-gpio.txt1 * Abilis TB10x GPIO controller
4 - compatible: Should be "abilis,tb10x-gpio"
5 - reg: Address and length of the register set for the device
6 - gpio-controller: Marks the device node as a gpio controller.
7 - #gpio-cells: Should be <2>. The first cell is the pin number and the
9 - bit 0 specifies polarity (0 for normal, 1 for inverted).
10 - abilis,ngpio: the number of GPIO pins this driver controls.
13 - interrupt-controller: Marks the device node as an interrupt controller.
14 - #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
15 - interrupts: Defines the interrupt line connecting this GPIO controller to
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Dgpio_atmel.txt1 * Atmel GPIO controller (PIO)
4 - compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
5 - reg: Should contain GPIO controller registers location and length
6 - interrupts: Should be the port interrupt shared by all the pins.
7 - #gpio-cells: Should be two. The first cell is the pin number and
8 the second cell is used to specify optional parameters to declare if the GPIO
9 is active high or low. See gpio.txt.
10 - gpio-controller: Marks the device node as a GPIO controller.
11 - interrupt-controller: Marks the device node as an interrupt controller.
12 - #interrupt-cells: Should be two. The first cell is the pin number and the
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Dsnps,dw-apb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB GPIO controller
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
12 GPIO-controller properties as described in this bindings file.
15 - Hoan Tran <hoan@os.amperecomputing.com>
16 - Serge Semin <fancer.lancer@gmail.com>
20 pattern: "^gpio@[0-9a-f]+$"
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Dgpio-thunderx.txt1 Cavium ThunderX/OCTEON-TX GPIO controller bindings
4 - reg: The controller bus address.
5 - gpio-controller: Marks the device node as a GPIO controller.
6 - #gpio-cells: Must be 2.
7 - First cell is the GPIO pin number relative to the controller.
8 - Second cell is a standard generic flag bitfield as described in gpio.txt.
11 - compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used.
12 - interrupt-controller: Marks the device node as an interrupt controller.
13 - #interrupt-cells: Must be present and have value of 2 if
14 "interrupt-controller" is present.
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Dgpio-twl4030.txt1 twl4030 GPIO controller bindings
4 - compatible:
5 - "ti,twl4030-gpio" for twl4030 GPIO controller
6 - #gpio-cells : Should be two.
7 - first cell is the pin number
8 - second cell is used to specify optional parameters (unused)
9 - gpio-controller : Marks the device node as a GPIO controller.
10 - #interrupt-cells : Should be 2.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 The first cell is the GPIO number.
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Dtoshiba,gpio-visconti.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/toshiba,gpio-visconti.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba Visconti ARM SoCs GPIO controller
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
15 - const: toshiba,gpio-tmpv7708
20 "#gpio-cells":
23 gpio-ranges: true
25 gpio-controller: true
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Drockchip,gpio-bank.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip GPIO bank
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,gpio-bank
16 - rockchip,rk3188-gpio-bank0
27 - description: APB interface clock source
28 - description: GPIO debounce reference clock source
[all …]
Dmstar,msc313-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/mstar,msc313-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MStar/SigmaStar GPIO controller
10 - Daniel Palmer <daniel@thingy.jp>
14 pattern: "^gpio@[0-9a-f]+$"
18 - mstar,msc313-gpio
19 - sstar,ssd20xd-gpio
24 gpio-controller: true
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/Documentation/devicetree/bindings/pinctrl/
Dbrcm,iproc-gpio.txt1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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