Searched full:implementation (Results 1 – 25 of 614) sorted by relevance
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| /Documentation/crypto/ |
| D | architecture.rst | 103 the following implementations: AES-NI, assembler implementation, or
105 which cipher implementation is used? The answer to that question is the
106 priority number assigned to each cipher implementation by the kernel
109 implementations providing an implementation with that name and selects
110 the implementation with the highest priority.
113 implementation and thus does not want to rely on the priority-based
115 the cipher implementation to register a unique name in addition to
117 sure to refer to the intended cipher implementation.
133 - module: the kernel module providing the cipher implementation (or
136 - priority: the priority value of the cipher implementation
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| D | intro.rst | 43 The transformation implementation is an actual code or interface to
48 implementation. There can be multiple transformation objects associated
49 with a single transformation implementation. Each of those
52 consumer requests a transformation implementation. The consumer is then
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| /Documentation/arch/arm/samsung/ |
| D | gpio.rst | 2 Samsung GPIO implementation
8 This outlines the Samsung GPIO implementation and the architecture
15 The gpio implementation uses gpiolib as much as possible, only providing
27 implementation to configure pins as necessary.
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| /Documentation/networking/ |
| D | x25.rst | 8 write an X.25 implementation for Linux. My aim is to provide a complete X.25
15 I therefore decided to write the implementation such that as far as the
18 implementation of LAPB. Therefore the LAPB modules would be called by
22 To confuse matters a little, an 802.2 LLC implementation is also possible
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| D | sctp.rst | 8 implementation.
21 The initial project goal is to create an Linux kernel reference implementation
33 implementation and testing lksctp on IPv4.
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| D | ipsec.rst | 33 is implementation dependent.
35 Current IPComp implementation is indeed by the book, while as in practice
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| /Documentation/core-api/ |
| D | genericirq.rst | 28 The original implementation of interrupt handling in Linux uses the
33 a quite universal set for the ARM interrupt handler implementation in
42 During the implementation we identified another type:
51 This split implementation of high-level IRQ handlers allows us to
56 The original general IRQ implementation used hw_interrupt_type
76 flow handler implementation also makes it simple to provide
82 IRQ-flow implementation for 'level type' interrupts and add a
83 (sub)architecture specific 'edge type' implementation.
225 handle_level_irq provides a generic implementation for level-triggered
238 handle_fasteoi_irq provides a generic implementation for interrupts,
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| /Documentation/networking/caif/ |
| D | linux_caif.rst | 29 The implementation of CAIF is divided into:
32 * CAIF Core Protocol Implementation
59 Implementation chapter
75 The Core CAIF implementation contains:
77 - Simple implementation of CAIF.
92 Implementation. The support functions include:
94 - CFPKT CAIF Packet. Implementation of CAIF Protocol Packet. The
98 The CAIF Protocol implementation contains:
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| /Documentation/locking/ |
| D | futex-requeue-pi.rst | 16 Without requeue_pi, the glibc implementation of
20 implementation would wake the highest-priority waiter, and leave the
56 user space already holding the PI futex. The glibc implementation
81 The actual glibc implementation will likely test for PI and make the
86 Implementation chapter
106 to be requeued to a PI-aware futex. The implementation is the
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| /Documentation/driver-api/ |
| D | men-chameleon-bus.rst | 9 1.2 Limitations of the current implementation
27 This document describes the architecture and implementation of the MEN
34 implementation and does by no means describe the complete possibilities of MCB
37 Limitations of the current implementation
40 The current implementation is limited to PCI and PCIe based carrier devices
69 not handled by the MCB implementation.
98 The current implementation assigns exactly one memory and one IRQ resource
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| /Documentation/driver-api/media/drivers/ |
| D | rkisp1.rst | 31 - V12 supports a new CSI-host implementation but can still
32 also use the same implementation from V10
43 - V13 does not support the old CSI-host implementation anymore
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| D | pvrusb2.rst | 29 1. Low level wire-protocol implementation with the device.
31 2. I2C adaptor implementation and corresponding I2C client drivers
34 3. High level hardware driver implementation which coordinates all
53 implementation and interface isolated from each other. Thus while
110 implementation had to be completely different.
150 pvrusb2-i2c-core.[ch] - This module provides an implementation of a
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| /Documentation/userspace-api/media/dvb/ |
| D | legacy_dvb_apis.rst | 17 code implementation, as this section of the document was written
19 implementation.
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| /Documentation/networking/devlink/ |
| D | devlink-reload.rst | 34 implementation might require to perform another action alongside with
42 By default reload actions are not limited and driver implementation may
46 implementation to specific constraints.
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| /Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
23 T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24 their implementation lacks a memory-mapped MTIME register, thus not
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 35 - altr,implementation: Nios II core implementation, this should be "fast";
50 altr,implementation = "fast";
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| /Documentation/watchdog/ |
| D | mlx-wdt.rst | 31 Type 1 HW watchdog implementation exist in old systems and
33 Two types of HW implementation have also different register map.
35 Type 3 HW watchdog implementation can exist on all Mellanox systems
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| /Documentation/arch/arm/ |
| D | vlocks.rst | 119 ARM implementation
122 The current ARM implementation [2] contains some optimisations beyond
130 In the ARM implementation, this means that we can use a single load
159 implementation uses a simple loop of word-sized loads for this
166 implementation.
171 implementation removes many of the barriers which would be required
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,corstone1000.yaml | 34 implementation of the Corstone1000 in the MPS3 prototyping board. See
39 implementation of this system. See ARM ecosystems FVP's.
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| /Documentation/bpf/ |
| D | clang-notes.rst | 5 Clang implementation notes
8 This document provides more details specific to the Clang/LLVM implementation of the eBPF instructi…
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| D | ringbuf.rst | 5 This document describes BPF ring buffer design, API, and implementation details.
16 implementation.
24 also solved by having an MPSC implementation of ring buffer. The ordering
143 Design and Implementation
185 One interesting implementation bit, that significantly simplifies (and thus
186 speeds up as well) implementation of both producers and consumers is how data
196 ``bpf_ringbuf_commit()`` implementation will send a notification of new record
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| /Documentation/driver-api/iio/ |
| D | hw-consumer.rst | 7 software buffer for data. The implementation can be found under
21 As standard IIO device the implementation is based on IIO provider/consumer.
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| /Documentation/driver-api/soundwire/ |
| D | error_handling.rst | 15 and audio data. The current implementation only logs such errors.
62 that the Slave might behave in implementation-defined ways. The bus
63 implementation does not provide a recovery mechanism for such errors, Slave
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| /Documentation/timers/ |
| D | hrtimers.rst | 36 - the implementation of the current posix-timer subsystem on top of
78 hrtimer subsystem implementation details
106 implementation needed to keep an extra list of all armed absolute
112 scaling code from the posix-timer implementation - the clock can simply
147 the hrtimer implementation details in praxis, and we also ran the posix
170 hrtimers-based high-resolution clock implementation, so the hrtimers
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| /Documentation/driver-api/thermal/ |
| D | cpu-cooling-api.rst | 71 For a given processor implementation the primary factors are:
93 implementation specific processor support and characterisation
94 factors. Therefore, in initial implementation that contribution is
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