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/Documentation/devicetree/bindings/pinctrl/
Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
14 configurable bias, drive strength, schmitt trigger etc. The SoC has an
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
[all …]
Dstarfive,jh7110-sys-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
14 schmitt trigger etc.
21 - Jianlong Huang <jianlong.huang@starfivetech.com>
25 const: starfive,jh7110-sys-pinctrl
39 interrupt-controller: true
41 '#interrupt-cells':
[all …]
Dstarfive,jh7110-aon-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
14 schmitt trigger etc.
18 - Jianlong Huang <jianlong.huang@starfivetech.com>
22 const: starfive,jh7110-aon-pinctrl
33 interrupt-controller: true
35 '#interrupt-cells':
[all …]
Dsprd,sc9860-pinctrl.txt7 - compatible: Must be "sprd,sc9860-pinctrl".
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
12 - function: A string containing the name of the function, values must be
14 - drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
16 - input-schmitt-disable: Enable schmitt-trigger mode.
17 - input-schmitt-enable: Disable schmitt-trigger mode.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
[all …]
Dsprd,pinctrl.txt16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
40 - bias-pull-down
46 and set the pin sleep related configuration as "input-enable", which
48 input enable automatically.
54 "sprd,sleep-mode" property to set pin sleep mode.
[all …]
Dpincfg-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
[all …]
Dnxp,lpc1850-scu.txt2 --------------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-scu"
6 - reg : Address and length of the register set for the device
7 - clocks : Clock specifier (see clock bindings for details)
9 The lpc1850-scu driver uses the generic pin multiplexing and generic pin
10 configuration documented in pinctrl-bindings.txt.
13 - function
14 - pins
15 - bias-disable
16 - bias-pull-up
[all …]
Dnvidia,tegra-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
57 description: Pull-down/up setting to apply to the pin.
[all …]
Dmediatek,mt8192-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
[all …]
Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
[all …]
Dimg,pistachio-pinctrl.txt8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
22 - gpio-controller: Indicates the device is a GPIO controller.
[all …]
Dmediatek,mt6779-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Teng <andy.teng@mediatek.com>
11 - Sean Wang <sean.wang@kernel.org>
20 - mediatek,mt6779-pinctrl
21 - mediatek,mt6797-pinctrl
26 reg-names: true
28 gpio-controller: true
[all …]
Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
22 '#gpio-cells':
29 gpio-ranges:
[all …]
Dbitmain,bm1880-pinctrl.txt7 - compatible: Should be "bitmain,bm1880-pinctrl"
8 - reg: Offset and length of pinctrl space in SCTRL.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
17 includes pinmux and various pin configuration parameters, such as pull-up,
24 The following generic properties as defined in pinctrl-bindings.txt are valid
29 - pins: An array of strings, each string containing the name of a pin.
32 MIO0 - MIO111
34 - groups: An array of strings, each string containing the name of a pin
65 - function: An array of strings, each string containing the name of the
90 - bias-disable: No arguments. Disable pin bias.
[all …]
Dactions,s500-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
16 pinctrl-bindings.txt in this directory for common binding part and usage.
20 const: actions,s500-pinctrl
24 - description: GPIO Output + GPIO Input + GPIO Data
25 - description: Multiplexing Control
[all …]
Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
30 - description: APB interface clock source
32 clock-names:
[all …]
Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
[all …]
Dmediatek,mt8183-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
17 const: mediatek,mt8183-pinctrl
23 reg-names:
25 - const: iocfg0
26 - const: iocfg1
27 - const: iocfg2
[all …]
Dactions,s700-pinctrl.txt7 - compatible: Should be "actions,s700-pinctrl"
8 - reg: Should contain the register base address and size of
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
16 - interrupt-controller: Marks the device node as an interrupt controller.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
21 bindings/interrupt-controller/interrupts.txt
[all …]
Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
[all …]
Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
[all …]
Dmediatek,mt8365-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Bernhard Rosenkränzer <bero@baylibre.com>
18 const: mediatek,mt8365-pinctrl
23 mediatek,pctl-regmap:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
32 gpio-controller: true
[all …]
Dbrcm,bcm11351-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Ray Jui <rjui@broadcom.com>
12 - Scott Branden <sbranden@broadcom.com>
15 - $ref: pinctrl.yaml#
19 const: brcm,bcm11351-pinctrl
25 '-pins$':
[all …]
Dactions,s900-pinctrl.txt7 - compatible: Should be "actions,s900-pinctrl"
8 - reg: Should contain the register base address and size of
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
16 - interrupt-controller: Marks the device node as an interrupt controller.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
21 bindings/interrupt-controller/interrupts.txt
[all …]
Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
[all …]

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