Searched full:instruction (Results 1 – 25 of 195) sorted by relevance
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| /Documentation/virt/kvm/s390/ |
| D | s390-pv.rst | 26 the behavior of the SIE instruction. A new format 4 state description
48 of an instruction emulation by KVM, e.g. we can never inject a
63 Instruction emulation
65 With the format 4 state description for PVMs, the SIE instruction already
67 to interpret every instruction, but needs to hand some tasks to KVM;
71 Instruction Data Area (SIDA), the Interception Parameters (IP) and the
73 the instruction data, such as I/O data structures, are filtered.
74 Instruction data is copied to and from the SIDA when needed. Guest
78 Only GR values needed to emulate an instruction will be copied into this
82 the bytes of the instruction text, but with pre-set register values
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| /Documentation/bpf/ |
| D | bpf_licensing.rst | 11 http://www.tcpdump.org/papers/bpf-usenix93.pdf. The corresponding instruction
13 instruction set is now known as "classic BPF".
15 However an instruction set is a specification for machine-language interaction,
18 instruction set may enjoy no copyright protection.
20 * eBPF (extended BPF) instruction set continues to be BSD
22 In 2014, the classic BPF instruction set was significantly extended. We
23 typically refer to this instruction set as eBPF to disambiguate it from cBPF.
24 The eBPF instruction set is still BSD licensed.
29 Using the eBPF instruction set requires implementing code in both kernel space
52 The HW can choose to execute eBPF instruction natively and provide eBPF runtime
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| D | clang-notes.rst | 8 …cument provides more details specific to the Clang/LLVM implementation of the eBPF instruction set.
27 instruction, which is not supported by the Linux kernel verifier.
33 enabled. If a lower version for ``-mcpu`` is set, the only atomic instruction
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| D | linux-notes.rst | 8 …ment provides more details specific to the Linux kernel implementation of the eBPF instruction set.
20 by the verifier. Any programs with this instruction will fail to load
34 The following 64-bit immediate instruction specifies that a variable address,
49 <instruction-set.html#legacy-bpf-packet-access-instructions>`_,
70 instruction.
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| D | llvm_reloc.rst | 63 For example, the first relocation corresponds to the first instruction
81 Similarly, the second relocation is at ``.text`` offset ``0x18``, instruction 3,
117 For example, ``R_BPF_64_64`` relocation type is used for ``ld_imm64`` instruction.
137 Type ``R_BPF_64_32`` is used for call instruction. The call target section
195 so the ``call`` instruction offset is ``(0 + 0)/8 - 1 = -1``.
197 offset ``0x18``, so the ``call`` instruction offset is ``(0 + 0x18)/8 - 1 = 2``.
257 or offset fields of the instruction at load time with information
260 Field to patch is selected basing on the instruction class:
272 * Field-based - patch instruction with field related information, e.g.
273 change offset field of the BPF_LDX instruction to reflect offset
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| D | classic_vs_extended.rst | 45 native instruction set and let the rest being interpreted.
70 registers and BPF_CALL instruction will be JITed as single 'call' HW
71 instruction. This calling convention was picked to cover common call
218 eBPF is a general purpose RISC instruction set. Not every register and
219 every instruction are used during translation from original BPF to eBPF.
220 For example, socket filters are not using ``exclusive add`` instruction, but
231 described, it may be used as safe instruction set.
251 | operation code | source | instruction class |
255 Three LSB bits store instruction class which is one of:
348 | mode | size | instruction class |
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| /Documentation/arch/arm64/ |
| D | legacy_instructions.rst | 7 the architecture. The infrastructure code uses undefined instruction
9 the instruction execution in hardware.
18 Generates undefined instruction abort. Default for instructions that
25 usage of emulated instruction is traced as well as rate limited
38 The default mode depends on the status of the instruction in the
42 Note: Instruction emulation may not be possible in all cases. See
43 individual instruction notes for further information.
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| /Documentation/staging/ |
| D | lzo.rst | 22 the operands for the instruction, whose size and position depend on the
23 opcode and on the number of literals copied by previous instruction. The
59 After any instruction except the large literal copy, 0, 1, 2 or 3 literals
60 are copied before starting the next instruction. The number of literals that
61 were copied may change the meaning and behaviour of the next instruction. In
62 practice, only one instruction needs to know whether 0, less than 4, or more
65 generally encoded in the last two bits of the instruction but may also be
69 instruction may encode this distance (0001HLLL), it takes one LE16 operand
100 0..16 : follow regular instruction encoding, see below. It is worth
120 Instruction encoding::
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| /Documentation/trace/coresight/ |
| D | coresight.rst | 22 "Sources" generate a compressed stream representing the processor instruction
361 comparator with "_stext" and "_etext", essentially tracing any instruction
401 Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}
402 Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc
403 Instruction 0 0x8026B544 E3A03000 false MOV r3,#0
404 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]
405 Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]
406 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
407 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
408 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
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| /Documentation/trace/ |
| D | kprobes.rst | 38 any instruction in the kernel. A return probe fires when a specified
65 instruction and replaces the first byte(s) of the probed instruction
66 with a breakpoint instruction (e.g., int3 on i386 and x86_64).
68 When a CPU hits the breakpoint instruction, a trap occurs, the CPU's
74 Next, Kprobes single-steps its copy of the probed instruction.
75 (It would be simpler to single-step the actual instruction in place,
77 instruction. This would open a small time window when another CPU
80 After the instruction is single-stepped, Kprobes executes the
82 Execution then continues with the instruction following the probepoint.
88 register set, including instruction pointer. This operation requires
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| /Documentation/arch/arm/nwfpe/ |
| D | notes.rst | 11 often uses an stfe instruction to save f4 on the stack upon entry to a
12 function, and an ldfe instruction to restore it before returning.
18 This is a side effect of the stfe instruction. The double in f4 had to be
32 in extended precision, due to the stfe instruction used to save f4 in log(y).
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| /Documentation/bpf/standardization/ |
| D | instruction-set.rst | 5 BPF Instruction Set Specification, v1.0
8 This document specifies version 1.0 of the BPF instruction set.
100 Instruction encoding
103 BPF has two instruction encodings:
105 * the basic instruction encoding, which uses 64 bits to encode an instruction
106 * the wide instruction encoding, which appends a second 64-bit immediate (i.e.,
107 constant) value after the basic instruction for a total of 128 bits.
109 The fields conforming an encoded basic instruction are stored in the
147 instruction uses a 64-bit immediate value that is constructed as follows.
148 The 64 bits following the basic instruction contain a pseudo instruction
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| /Documentation/powerpc/ |
| D | dscr.rst | 64 works, as it is emulated following an illegal instruction exception
69 all mfspr instruction based read attempts will get emulated and returned
70 where as the first mtspr instruction based write attempts will enable
82 (1) mtspr instruction (SPR number 0x03)
83 (2) mtspr instruction (SPR number 0x11)
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| D | syscall64-abi.rst | 10 The syscall is made with the sc instruction, and returns with execution
11 continuing at the instruction following the sc instruction.
14 scv 0 instruction is an alternative that may provide better performance,
32 - For the sc instruction, both a value and an error condition are returned.
38 - For the scv 0 instruction, the return value indicates failure if it is
52 For the sc instruction, the differences from the ELF ABI are as follows:
70 For the scv 0 instruction, the differences from the ELF ABI are as follows:
119 performed with the sc instruction, if it is 0x3000 then the system call was
120 performed with the scv 0 instruction.
147 The vsyscall is performed with a branch-with-link instruction to the vsyscall
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| D | elf_hwcaps.rst | 110 The timebase facility (mftb instruction) is not available.
136 The processor icache is coherent with the dcache, and instruction storage
139 User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi))::
194 isel instruction is available. This is superseded by ARCH_2_07 and
216 darn instruction is available.
219 The scv 0 instruction may be used for system calls, see
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| D | isa-versions.rst | 24 Power5 - PowerPC User Instruction Set Architecture Book I v2.02
27 PPC970 - PowerPC User Instruction Set Architecture Book I v2.01
31 Power4+ - PowerPC User Instruction Set Architecture Book I v2.01
34 Power4 - PowerPC User Instruction Set Architecture Book I v2.00
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| /Documentation/devicetree/bindings/watchdog/ |
| D | microchip,pic32-dmt.txt | 4 malfunction. It is a free-running instruction fetch timer, which is clocked
5 whenever an instruction fetch occurs until a count match occurs.
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| /Documentation/ABI/testing/ |
| D | debugfs-driver-dcc | 41 i) Read instruction
61 ii) Write instruction
78 iii) Read-write instruction
95 iv) Loop instruction
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| /Documentation/filesystems/spufs/ |
| D | spu_run.rst | 28 uled to a physical SPU, it starts execution at the instruction pointer
37 When spu_run returns, the current value of the SPU instruction pointer
62 optionally a 14 bit code returned from the stop-and-signal instruction
78 SPU has tried to execute an invalid instruction.
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 18 - icache-line-size: Contains instruction line size.
20 - icache-size: Contains instruction cache size.
28 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
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| /Documentation/arch/arm/ |
| D | swp_emulation.rst | 1 Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
8 instructions, triggering an undefined instruction exception when executed.
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 12 instruction set, virtual memory and some other topics of LoongArch.
27 link register of the BL instruction.)
109 0x8 Bad (Faulting) Instruction Word BADI
180 0x380 Instruction Fetch WatchPoint FWPC
182 0x381 Instruction Fetch WatchPoint FWPS
184 0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1
186 0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2
188 0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3
190 0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4
200 Basic Instruction Set
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| /Documentation/virt/kvm/x86/ |
| D | hypercalls.rst | 9 instruction. The hypervisor can replace it with instructions that are
21 S390 uses diagnose instruction as hypercall (0x500) along with hypercall
36 KVM hypercalls use the HYPCALL instruction with code 0 and the hypercall
95 execute HLT instruction once it has busy-waited for more than a threshold
96 time-interval. Execution of HLT instruction would cause the hypervisor to put
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| /Documentation/arch/x86/ |
| D | tlb.rst | 10 1. Flush the entire TLB with a two-instruction sequence. This is
14 2. Use the invlpg instruction to invalidate a single page at a
42 invlpg instruction (or instructions _near_ it) show up high in
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| /Documentation/arch/parisc/ |
| D | debugging.rst | 41 was interrupted - so if you get an interruption between the instruction
44 instruction that cleared the Q bit, if you're not it points anywhere
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