Searched +full:int +full:- +full:fwd +full:- +full:mask (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 210 - Florian Fainelli <f.fainelli@gmail.com>14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based19 - outputs multiple interrupts signals towards its interrupt controller parent21 - controls how some of the interrupts will be flowing, whether they will26 - has one 32-bit enable word and one 32-bit status word[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Broadcom BCM7038-style Level 1 interrupt controller11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip16 - 64, 96, 128, or 160 incoming level IRQ lines18 - Most onchip peripherals are wired directly to an L1 input20 - A separate instance of the register set for each CPU, allowing individual23 - Atomic mask/unmask operations[all …]