Searched full:integers (Results 1 – 25 of 96) sorted by relevance
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx6sx-pinctrl.txt | 8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx6ul-pinctrl.txt | 9 - fsl,pins: each entry consists of 6 integers and represents the mux and config
10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx6sll-pinctrl.txt | 8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx7ulp-pinctrl.txt | 15 - fsl,pins: Each entry consists of 5 integers which represents the mux
16 and config setting for one pin. The first 4 integers
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| D | fsl,scu-pinctrl.yaml | 37 each entry consists of 3 integers and represents the pin ID, the mux value
38 and pad setting for the pin. The first 2 integers - pin_id and mux_val - are
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| D | fsl,imxrt1170.yaml | 35 each entry consists of 6 integers and represents the mux and config
36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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| D | fsl,imxrt1050.yaml | 35 each entry consists of 6 integers and represents the mux and config
36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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| D | fsl,imx93-pinctrl.yaml | 37 each entry consists of 6 integers and represents the mux and config
38 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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| D | fsl,imx8ulp-pinctrl.yaml | 34 each entry consists of 5 integers and represents the mux and config
35 setting for one pin. The first 4 integers <mux_config_reg input_reg
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| D | fsl,imx8m-pinctrl.yaml | 38 each entry consists of 6 integers and represents the mux and config
39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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| D | fsl,imx7d-pinctrl.yaml | 43 each entry consists of 6 integers and represents the mux and config
44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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| D | fsl,imx-pinctrl.txt | 25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx53-pinctrl.txt | 8 - fsl,pins: two integers array, represents a group of pins mux and config
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| D | fsl,imx51-pinctrl.txt | 8 - fsl,pins: two integers array, represents a group of pins mux and config
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| D | fsl,imx50-pinctrl.txt | 8 - fsl,pins: two integers array, represents a group of pins mux and config
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| D | fsl,imx35-pinctrl.txt | 8 - fsl,pins: two integers array, represents a group of pins mux and config
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| D | fsl,imx6q-pinctrl.txt | 8 - fsl,pins: two integers array, represents a group of pins mux and config
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| D | fsl,imx6dl-pinctrl.txt | 8 - fsl,pins: two integers array, represents a group of pins mux and config
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | ts4800-ts.txt | 7 - syscon: phandle / integers array that points to the syscon node which
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| /Documentation/ABI/testing/ |
| D | sysfs-class-chromeos-driver-cros-ec-lightbar | 37 The values written to this file are sets of four integers,
43 more than one set of four integers.
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| D | sysfs-class-led-multicolor | 19 This file contains array of integers. Order of components is
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| D | sysfs-driver-hid-lenovo | 41 Values are decimal integers from 1 (lowest sensitivity) to 255 (highest sensitivity).
49 Values are decimal integers from 1 (slowest) to 255 (fastest).
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-netxbig.txt | 9 - timers: Timer array. Each timer entry is represented by three integers:
16 - mode-val: Mode to value mapping. Each entry is represented by two integers:
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| /Documentation/dev-tools/ |
| D | sparse.rst | 28 which makes PM_SUSPEND and PM_RESUME "bitwise" integers (the "__force" is
35 ends up looking just like integers to gcc.
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| /Documentation/devicetree/bindings/hwmon/ |
| D | ltc2990.txt | 7 An array of two integers for configuring the chip measurement mode.
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