Searched full:interrupts (Results 1 – 25 of 2675) sorted by relevance
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| /Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 21 - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal
22 sources; the interrupts are ordered in 3 groups, as follows:
23 - Phy interrupts
24 - Completion queue interrupts
25 - Fatal interrupts
26 Phy interrupts : Each phy has 3 interrupt sources:
30 The phy interrupts are ordered into groups of 3 per phy
32 Completion queue interrupts : each completion queue has 1
34 The interrupts are ordered in increasing order.
35 Fatal interrupts : the fatal interrupts are ordered as follows:
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | samsung,pinctrl-wakeup-interrupt.yaml | 18 External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller.
21 interrupts child node (in other words, only one External wake-up interrupts
24 external wake-up interrupts child node.
41 interrupts:
43 Interrupt used by multiplexed external wake-up interrupts.
60 interrupts:
64 - interrupts
73 interrupts:
77 - interrupts
89 interrupts:
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| D | samsung,pinctrl-gpio-bank.yaml | 31 For GPIO banks supporting external GPIO interrupts or external wake-up
32 interrupts.
37 For GPIO banks supporting external GPIO interrupts or external wake-up
38 interrupts.
40 interrupts:
42 For GPIO banks supporting direct external wake-up interrupts (without
43 multiplexing). Number of interrupts must match number of wake-up capable
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| D | samsung,pinctrl.yaml | 21 The controller supports three types of interrupts::
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
28 - External wake-up interrupts - direct (capable of waking up the system, see
29 interrupts property in every bank of pin controller with external wake-up
58 interrupts:
60 Required for GPIO banks supporting external GPIO interrupts.
145 interrupts = <21>;
149 interrupts-extended = <&vic0 0>,
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 19 - interrupts : Should be single bit error interrupt, then double bit error
27 - interrupts : Should be single bit error interrupt, then double bit error
41 interrupts = <0 36 1>, <0 37 1>;
48 interrupts = <0 178 1>, <0 179 1>;
63 - interrupts : Should be single bit error interrupt, then double bit error
75 - interrupts : Should be single bit error interrupt, then double bit error
82 - interrupts : Should be single bit error interrupt, then double bit error
90 - interrupts : Should be single bit error interrupt, then double bit error
98 - interrupts : Should be single bit error interrupt, then double bit error
106 - interrupts : Should be single bit error interrupt, then double bit error
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | microchip,pic32-evic.txt | 5 It handles all internal and external interrupts. This controller exists outside
6 of the CPU and is the arbitrator of all interrupts (including interrupts from
9 External interrupts have a software configurable edge polarity. Non external
10 interrupts have a type and polarity that is determined by the source of the
27 internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
28 IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
33 - microchip,external-irqs: u32 array of external interrupts with software
56 interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
65 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
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| D | ti,pruss-intc.yaml | 15 which are then mapped to 10 possible output interrupts through two levels
18 interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
23 differences on the output interrupts 2 through 9. If this property is not
24 defined, it implies that all the PRUSS INTC output interrupts 2 through 9
29 different possible output interrupts. The additional output interrupts (10
54 interrupts:
58 All the interrupts generated towards the main host processor in the SoC.
79 host_event (target) [cell 3] as the value of the interrupts property in
81 interrupts through 2 levels of many-to-one mapping i.e. events to channel
82 mapping and channels to host interrupts so through this property entire
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| D | riscv,cpu-intc.txt | 6 Some of these CSRs are used to control local interrupts connected to the core.
8 interrupts that hart.
11 attached to every HLIC: software interrupts, the timer interrupt, and external
12 interrupts. Software interrupts are used to send IPIs between cores. The
15 interrupts connect all other device interrupts to the HLIC, which are routed
22 need to define how their interrupts map to the relevant HLICs. This means
29 RISC-V supervisor ISA manual, with only the following three interrupts being
36 device interrupts.
40 definition of the hart whose CSRs control these local interrupts.
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| D | interrupts.txt | 7 Nodes that describe devices which generate interrupts must contain an
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
13 which the interrupts are routed; see section 2 below for details.
17 interrupts = <5 0>, <6 0>;
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
64 interrupts = <31>; /* Cascaded to vic */
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| D | snps,dw-apb-ictl.txt | 16 - interrupts: interrupt reference to primary interrupt controller
20 - 0 maps to bit 0 of low interrupts,
21 - 1 maps to bit 1 of low interrupts,
22 - 32 maps to bit 0 of high interrupts,
23 - 33 maps to bit 1 of high interrupts,
24 - (optional) fast interrupts start at 64.
34 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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| D | marvell,orion-intc.txt | 22 /* Dove has 64 first level interrupts */
31 - interrupts: bridge interrupt of the main interrupt controller
36 - marvell,#interrupts: number of interrupts provided by bridge interrupt
45 interrupts = <0>;
46 /* Dove bridge provides 5 interrupts */
47 marvell,#interrupts = <5>;
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| D | loongson,htvec.yaml | 14 receiving vectorized interrupts from PCH's interrupt controller.
23 interrupts:
26 description: Eight parent interrupts that receive chained interrupts.
36 - interrupts
52 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
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| D | loongson,htpic.yaml | 17 interrupts from PCH PIC connected on HyperTransport bus.
26 interrupts:
30 Four parent interrupts that receive chained interrupts.
40 - interrupts
56 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
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| /Documentation/devicetree/bindings/timer/ |
| D | nvidia,tegra-timer.yaml | 20 interrupts:
21 # Either a single combined interrupt or up to 14 individual interrupts
25 A list of 14 interrupts; one per each timer channels 0 through 13
42 interrupts:
43 # Either a single combined interrupt or up to 6 individual interrupts
47 A list of 6 interrupts; one per each of timer channels 1 through 5,
56 interrupts:
57 # Either a single combined interrupt or up to 4 individual interrupts
61 A list of 4 interrupts; one per timer channel.
72 or watchdog interrupts.
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| D | samsung,exynos4210-mct.yaml | 15 up-counter and can generate 4 interrupts when the counter reaches one of the
62 interrupts:
64 Interrupts should be put in specific order. This is, the local timer
65 interrupts should be specified after the four global timer interrupts
87 - interrupts
109 interrupts:
120 interrupts:
136 interrupts:
148 interrupts:
157 // interrupts, so two local timer interrupts have been specified,
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| D | allwinner,sun4i-a10-timer.yaml | 32 interrupts:
36 List of timers interrupts
50 interrupts:
62 interrupts:
75 interrupts:
82 - interrupts
92 interrupts = <22>,
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| /Documentation/devicetree/bindings/usb/ |
| D | twlxxxx-usb.txt | 5 - interrupts : Two interrupt numbers to the cpu should be specified. First
6 interrupt number is the otg interrupt number that raises ID interrupts when
8 usb interrupt number that raises VBUS interrupts when the controller has to
15 interrupts = < 4 10 >;
25 - interrupts : The interrupt numbers to the cpu should be specified. First
26 interrupt number is the otg interrupt number that raises ID interrupts
27 and VBUS interrupts. The second interrupt number is optional.
38 interrupts = < 10 4 >;
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 15 - interrupts : interrupt specifier for DMA IRQ
24 - interrupts : interrupt specifier for DMA channel IRQ
26 the interrupts property of the parent node)
36 interrupts = <71 8>;
43 interrupts = <71 8>;
50 interrupts = <71 8>;
57 interrupts = <71 8>;
64 interrupts = <71 8>;
88 - interrupts : interrupt specifier for DMA channel IRQ
103 interrupts = <20 2>;
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| D | mpic-msgr.txt | 18 - interrupts: Specifies a list of interrupt-specifiers which are available
19 for receiving interrupts. Interrupt-specifier consists of two cells: first
26 are allowed to receive interrupts. The value is a bit mask where a set
27 bit at bit 'n' indicates that message register 'n' can receive interrupts.
50 // Message registers 0 and 2 in this block can receive interrupts on
52 interrupts = <0xb0 2 0xb2 2>;
59 // Message registers 0 and 2 in this block can receive interrupts on
61 interrupts = <0xb4 2 0xb6 2>;
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| /Documentation/devicetree/bindings/net/ |
| D | maxlinear,gpy2xx.yaml | 17 maxlinear,use-broken-interrupts:
19 Interrupts are broken on some GPY2xx PHYs in that they keep the
23 interrupts are disabled for this PHY and polling mode is used. If one
31 maxlinear,use-broken-interrupts: [ interrupts ]
43 interrupts-extended = <&intc 0>;
44 maxlinear,use-broken-interrupts;
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| /Documentation/devicetree/bindings/counter/ |
| D | interrupt-counter.yaml | 17 Interrupts or gpios are required. If both are defined, the interrupt will
18 take precedence for counting interrupts.
24 interrupts:
34 - required: [ interrupts-extended ]
35 - required: [ interrupts ]
48 interrupts-extended = <&gpio 0 IRQ_TYPE_EDGE_RISING>;
58 interrupts-extended = <&gpio 2 IRQ_TYPE_EDGE_RISING>;
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| /Documentation/virt/kvm/devices/ |
| D | s390_flic.rst | 7 FLIC handles floating (non per-cpu) interrupts, i.e. I/O, service and some
8 machine check interruptions. All interrupts are stored in a per-vm list of
9 pending interrupts. FLIC performs operations on this list.
14 - add interrupts (KVM_DEV_FLIC_ENQUEUE)
15 - inspect currently pending interrupts (KVM_FLIC_GET_ALL_IRQS)
16 - purge all pending floating interrupts (KVM_DEV_FLIC_CLEAR_IRQS)
21 - inject adapter interrupts on a specified adapter (KVM_DEV_FLIC_AIRQ_INJECT)
27 the list of pending interrupts.
34 Copies all floating interrupts into a buffer provided by userspace.
42 All interrupts remain pending, i.e. are not deleted from the list of
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| /Documentation/devicetree/bindings/regulator/ |
| D | qcom-labibb-regulator.yaml | 32 interrupts:
36 Short-circuit and over-current interrupts for lab.
45 - interrupts
60 interrupts:
64 Short-circuit and over-current interrupts for ibb.
73 - interrupts
89 interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
95 interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
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| /Documentation/devicetree/bindings/gpio/ |
| D | brcm,kona-gpio.yaml | 12 GPIO controller only supports edge, not level, triggering of interrupts.
29 interrupts:
34 per GPIO bank. The number of interrupts listed depends on the number of
35 GPIO banks on the SoC. The interrupts must be ordered by bank, starting
51 - interrupts
65 interrupts:
76 interrupts:
89 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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| /Documentation/devicetree/bindings/phy/ |
| D | rockchip,inno-usb2phy.yaml | 56 interrupts:
83 interrupts:
106 interrupts:
152 interrupts: false
156 interrupts: false
159 - interrupts
163 interrupts: false
167 - interrupts
172 - interrupts
191 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
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