Searched full:memories (Results 1 – 25 of 44) sorted by relevance
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-peripheral-props.yaml | 91 stacked-memories:
92 description: Several SPI memories can be wired in stacked mode.
103 parallel-memories:
104 description: Several SPI memories can be wired in parallel mode.
107 different memories (eg. even bits are stored in one memory, odd
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| D | socionext,f-ospi.yaml | 11 memories using the SPI communication interface.
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| D | amlogic,meson6-spifc.yaml | 18 NOR memories, without DMA support and a 64-byte unified transmit /
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| /Documentation/arch/arm/stm32/ |
| D | stm32mp13-overview.rst | 12 - Standard memories interface support
19 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32mp151-overview.rst | 12 - Standard memories interface support
19 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32mp157-overview.rst | 13 - Standard memories interface support
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| D | stm32h743-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32h750-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32f746-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32f769-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 61 memories are placed into power-down mode if bus is idle for PD_IDLE DFI
70 which memories are placed into self-refresh mode if bus is idle for
80 Memories are placed into self-refresh mode and memory controller clock
89 Defines the self-refresh power down idle period in which memories are
99 Defines the standby idle period in which memories are placed into
288 period in which memories are placed into power-down mode if bus is idle
294 period in which memories are placed into self-refresh mode if bus is idle
301 Memories are placed into self-refresh mode and memory controller clock
306 Defines the self-refresh power down idle period in which memories are
312 Defines the standby idle period in which memories are placed into
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| D | atmel,ebi.txt | 4 asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
5 The EBI provides a glue-less interface to asynchronous memories through the SMC
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | xlnx,zynqmp-r5fss.yaml | 45 tightly coupled memories (TCM). System memory is cacheable, but the TCM
48 Each RPU contains one 64KB memory and two 32KB memories that
81 the main DDR memory, and other system memories.
90 remoteproc device. This is variable and describes the memories shared with
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| D | renesas,rcar-rproc.yaml | 31 remoteproc device. This is variable and describes the memories shared with
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| D | st,stm32-rproc.yaml | 23 Address ranges of the RETRAM and MCU SRAM memories used by the remote
100 remoteproc device. This is variable and describes the memories shared with
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| D | ti,pru-rproc.yaml | 121 pruss_mem: memories@0 {
160 icssg0_mem: memories@0 {
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,pruss.yaml | 34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
51 processor cores, the memories node, an INTC node and an MDIO node represented
97 memories@[a-f0-9]+$:
100 single node with the name 'memories'.
318 # - memories
357 pruss_mem: memories@0 {
441 pruss1_mem: memories@0 {
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| /Documentation/hwmon/ |
| D | pm6764tr.rst | 23 performance digital controller designed to power Intel's VR12.5 processors and memories.
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,imx7ulp-pm.yaml | 16 controlling the power, clocks, and memories of the MCU to achieve the
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-edac | 93 of the DIMM memory stick. On single rank memories (1R), this
94 is also the total size of the dimm. On dual rank (2R) memories,
95 this is half the size of the total DIMM memories.
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| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | imx8m-ddrc.yaml | 14 memories.
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| /Documentation/arch/arm/ |
| D | tcm.rst | 19 location and size of TCM memories. arch/arm/include/asm/cputype.h
29 size of TCM memories at runtime. This is used to read out and modify
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| /Documentation/devicetree/bindings/arm/stm32/ |
| D | st,mlahb.yaml | 15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
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| /Documentation/driver-api/memory-devices/ |
| D | ti-emif.rst | 31 This driver takes care of only LPDDR2 memories presently. The
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| /Documentation/devicetree/bindings/bus/ |
| D | qcom,ebi2.txt | 10 NOR flash memories), WE (write enable). This on top of 6 different chip selects
39 flag somewhere for 8bit memories.
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