Searched +full:memory +full:- +full:region (Results 1 – 25 of 395) sorted by relevance
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | memory-region.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/memory-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Reserved Memory Region
10 - devicetree-spec@vger.kernel.org
13 Regions in the /reserved-memory node may be referenced by other device
14 nodes by adding a memory-region property to the device node.
19 memory-region:
20 $ref: /schemas/types.yaml#/definitions/phandle-array
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| D | reserved-memory.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/reserved-memory.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory Child Node Common
10 - devicetree-spec@vger.kernel.org
13 Reserved memory is specified as a node under the /reserved-memory node. The
14 operating system shall exclude reserved memory from normal usage one can
16 memory regions. Such memory regions are usually designed for the special
19 Each child of the reserved-memory node specifies one or more regions
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| D | xen,shared-memory.txt | 1 * Xen hypervisor reserved-memory binding
3 Expose one or more memory regions as reserved-memory to the guest
4 virtual machine. Typically, a region is configured at VM creation time
5 to be a shared memory area across multiple virtual machines for
8 For each of these pre-shared memory regions, a range is exposed under
9 the /reserved-memory node as a child node. Each range sub-node is named
10 xen-shmem@<address> and has the following properties:
12 - compatible:
13 compatible = "xen,shared-memory-v1"
15 - reg:
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| D | shared-dma-pool.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/shared-dma-pool.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory DMA pool
10 - devicetree-spec@vger.kernel.org
13 - $ref: reserved-memory.yaml
18 - const: shared-dma-pool
20 This indicates a region of memory meant to be used as a shared
25 - const: restricted-dma-pool
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| D | nvidia,tegra264-bpmp-shmem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra CPU-NS - BPMP IPC reserved memory
10 - Peter De Schrijver <pdeschrijver@nvidia.com>
13 Define a memory region used for communication between CPU-NS and BPMP.
15 has to be known to both CPU-NS and BPMP for correct IPC operation.
16 The memory region is defined using a child node under /reserved-memory.
17 The sub-node is named shmem@<address>.
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| /Documentation/devicetree/bindings/pmem/ |
| D | pmem-region.txt | 1 Device-tree bindings for persistent memory regions
2 -----------------------------------------------------
4 Persistent memory refers to a class of memory devices that are:
6 a) Usable as main system memory (i.e. cacheable), and
9 Given b) it is best to think of persistent memory as a kind of memory mapped
11 persistent regions separately to the normal memory pool. To aid with that this
13 memory regions exist inside the physical address space.
15 Bindings for the region nodes:
16 -----------------------------
19 - compatible = "pmem-region"
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt7622-wed.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
21 - enum:
22 - mediatek,mt7622-wed
23 - mediatek,mt7981-wed
24 - mediatek,mt7986-wed
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory Manager
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 This binding describes the Qualcomm Shared Memory Manager, a region of
15 reserved-memory used to share data between various subsystems and OSes in
25 memory-region:
27 description: handle to memory reservation for main SMEM memory region.
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| /Documentation/devicetree/bindings/media/ |
| D | aspeed-video.txt | 7 - compatible: "aspeed,ast2400-video-engine" or
8 "aspeed,ast2500-video-engine" or
9 "aspeed,ast2600-video-engine"
10 - reg: contains the offset and length of the VE memory region
11 - clocks: clock specifiers for the syscon clocks associated with
12 the VE (ordering must match the clock-names property)
13 - clock-names: "vclk" and "eclk"
14 - resets: reset specifier for the syscon reset associated with
16 - interrupts: the interrupt associated with the VE on this platform
19 - memory-region:
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| D | amphion,vpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,davinci-rproc.txt | 4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
11 The processor cores in the sub-system usually contain additional sub-modules
12 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
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| D | ti,k3-dsp-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
18 L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
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| D | qcom,sm8550-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sm8550-adsp-pas
20 - qcom,sm8550-cdsp-pas
21 - qcom,sm8550-mpss-pas
28 - description: XO clock
30 clock-names:
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| D | qcom,msm8916-mss-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
19 - enum:
20 - qcom,msm8909-mss-pil
21 - qcom,msm8916-mss-pil
22 - qcom,msm8953-mss-pil
23 - qcom,msm8974-mss-pil
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| D | qcom,msm8996-mss-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Sibi Sankar <quic_sibis@quicinc.com>
20 - qcom,msm8996-mss-pil
21 - qcom,msm8998-mss-pil
22 - qcom,sdm660-mss-pil
23 - qcom,sdm845-mss-pil
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| /Documentation/PCI/endpoint/ |
| D | pci-ntb-function.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
12 machine, expose memory ranges as BARs, and perform DMA. They also support
13 scratchpads, which are areas of memory within the NTB that are accessible
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
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| /Documentation/arch/arm64/ |
| D | kdump.rst | 2 crashkernel memory reservation on arm64
9 reserved memory is needed to pre-load the kdump kernel and boot such
12 That reserved memory for kdump is adapted to be able to minimally
19 Through the kernel parameters below, memory can be reserved accordingly
21 large chunk of memomy can be found. The low memory reservation needs to
22 be considered if the crashkernel is reserved from the high memory area.
24 - crashkernel=size@offset
25 - crashkernel=size
26 - crashkernel=size,high crashkernel=size,low
28 Low memory and high memory
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-cxl | 4 Contact: linux-cxl@vger.kernel.org
14 Contact: linux-cxl@vger.kernel.org
17 Memory Device Output Payload in the CXL-2.0
24 Contact: linux-cxl@vger.kernel.org
27 identically named field in the Identify Memory Device Output
28 Payload in the CXL-2.0 specification.
34 Contact: linux-cxl@vger.kernel.org
37 identically named field in the Identify Memory Device Output
38 Payload in the CXL-2.0 specification.
44 Contact: linux-cxl@vger.kernel.org
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
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| /Documentation/devicetree/bindings/cache/ |
| D | qcom,llcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
16 common pool of memory. Cache memory is divided into partitions called slices
23 - qcom,sc7180-llcc
24 - qcom,sc7280-llcc
25 - qcom,sc8180x-llcc
26 - qcom,sc8280xp-llcc
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| /Documentation/devicetree/bindings/gpu/ |
| D | aspeed-gfx.txt | 4 - compatible
6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
11 - reg: Physical base address and length of the GFX registers
13 - interrupts: interrupt number for the GFX device
15 - clocks: clock number used to generate the pixel clock
17 - resets: reset line that must be released to use the GFX device
19 - memory-region:
20 Phandle to a memory region to allocate from, as defined in
21 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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| /Documentation/devicetree/bindings/sound/ |
| D | google,cros-ec-codec.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/sound/google,cros-ec-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cheng-Yi Chiang <cychiang@chromium.org>
11 - Tzung-Bi Shih <tzungbi@kernel.org>
15 Embedded Controller (EC) and is controlled via a host-command
17 subnode of a cros-ec node.
18 (see Documentation/devicetree/bindings/mfd/google,cros-ec.yaml).
21 - $ref: dai-common.yaml#
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| /Documentation/admin-guide/mm/damon/ |
| D | reclaim.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 DAMON-based Reclamation
7 DAMON-based Reclamation (DAMON_RECLAIM) is a static kernel module that aimed to
8 be used for proactive and lightweight reclamation under light memory pressure.
9 It doesn't aim to replace the LRU-list based page_granularity reclamation, but
10 to be selectively used for different level of memory pressure and requirements.
15 On general memory over-committed systems, proactively reclaiming cold pages
16 helps saving memory and reducing latency spikes that incurred by the direct
20 Free Pages Reporting [3]_ based memory over-commit virtualization systems are
22 memory to host, and the host reallocates the reported memory to other guests.
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| /Documentation/devicetree/bindings/mtd/ |
| D | arm,pl353-nand-r2p1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/arm,pl353-nand-r2p1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml
13 - Miquel Raynal <miquel.raynal@bootlin.com>
18 - const: arm,pl353-nand-r2p1
22 - items:
23 - description: CS with regard to the parent ranges property
24 - description: Offset of the memory region requested by the device
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| /Documentation/mm/damon/ |
| D | design.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 - Operations Set: Implements fundamental operations for DAMON that depends on
14 the given monitoring target address-space and available set of
16 - Core: Implements core logics including monitoring overhead/accurach control
17 and access-aware system operations on top of the operations set layer, and
18 - Modules: Implements kernel modules for various purposes that provides
23 ---------------------------
38 For example, physical memory, virtual memory, swap space, those for specific
39 processes, NUMA nodes, files, and backing memory devices would be supportable.
45 --------------------
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