Searched +full:multi +full:- +full:address (Results 1 – 25 of 214) sorted by relevance
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| /Documentation/userspace-api/media/v4l/ |
| D | planar-apis.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _planar-apis:
6 Single- and multi-planar APIs
11 has to be addressed using more than one memory address, i.e. one pointer
12 per "plane". A plane is a sub-buffer of the current frame. For examples
15 Initially, V4L2 API did not support multi-planar buffers and a set of
17 constitute what is being referred to as the "multi-planar API".
20 depending on whether single- or multi-planar API is being used. An
22 corresponding buffer type to its ioctl calls. Multi-planar versions of
24 available multi-planar buffer types see enum
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| D | func-mmap.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _func-mmap:
13 v4l2-mmap - Map device memory into application address space
18 .. code-block:: c
29 Map the buffer to this address in the application's address space.
32 address cannot be used. Use of this option is discouraged;
39 single-planar API, and the same value as returned by the driver in
41 the multi-planar API.
69 ``MAP_FIXED`` requests that the driver selects no other address than
70 the one specified. If the specified address cannot be used,
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsl-upm-nand.txt | 4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
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| D | mxic-nand.txt | 2 -------------------------------------------------
5 - compatible: should be "mxic,multi-itfc-v009-nand-controller"
6 - reg: should contain 1 entry for the registers
7 - #address-cells: should be set to 1
8 - #size-cells: should be set to 0
9 - interrupts: interrupt line connected to this raw NAND controller
10 - clock-names: should contain "ps", "send" and "send_dly"
11 - clocks: should contain 3 phandles for the "ps", "send" and
15 - children nodes represent the available NAND chips.
17 See Documentation/devicetree/bindings/mtd/nand-controller.yaml
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp50xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp50xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Davis <afd@ti.com>
13 The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into
27 - ti,lp5009
28 - ti,lp5012
29 - ti,lp5018
30 - ti,lp5024
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| D | cznic,turris-omnia-leds.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/leds/cznic,turris-omnia-leds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
20 const: cznic,turris-omnia-leds
23 description: I2C slave address of the microcontroller.
26 "#address-cells":
29 "#size-cells":
33 "^multi-led@[0-9a-b]$":
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| D | leds-qcom-lpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
20 - enum:
21 - qcom,pm660l-lpg
22 - qcom,pm8150b-lpg
23 - qcom,pm8150l-lpg
24 - qcom,pm8350c-pwm
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| D | mediatek,mt6370-indicator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/mediatek,mt6370-indicator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alice Chen <alice_chen@richtek.com>
14 Add MT6370 LED driver include 4-channel RGB LED support Register/PWM/Breath Mode
18 const: mediatek,mt6370-indicator
20 "#address-cells":
23 "#size-cells":
27 "^multi-led@[0-3]$":
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | m4if.txt | 1 * Freescale Multi Master Multi Memory Interface (M4IF) module
4 - compatible : Should be "fsl,imx51-m4if"
5 - reg : Address and length of the register set for the device
10 compatible = "fsl,imx51-m4if";
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| /Documentation/devicetree/bindings/sound/ |
| D | sprd-mcdt.txt | 1 Spreadtrum Multi-Channel Data Transfer Binding
3 The Multi-channel data transfer controller is used for sound stream
9 - compatible: Should be "sprd,sc9860-mcdt".
10 - reg: Should contain registers address and length.
11 - interrupts: Should contain one interrupt shared by all channel.
16 compatible = "sprd,sc9860-mcdt";
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| /Documentation/devicetree/bindings/mfd/ |
| D | brcm,iproc-mhb.txt | 1 Broadcom iProc Multi Host Bridge (MHB)
3 Certain Broadcom iProc SoCs have a multi host bridge (MHB) block that controls
10 - compatible: should contain:
11 "brcm,sr-mhb", "syscon" for Stingray
12 - reg: base address and range of the MHB registers
16 compatible = "brcm,sr-mhb", "syscon";
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| D | retu.txt | 1 * Device tree bindings for Nokia Retu and Tahvo multi-function device
3 Retu and Tahvo are a multi-function devices found on Nokia Internet
9 - compatible: "nokia,retu" or "nokia,tahvo"
10 - reg: Specifies the CBUS slave address of the ASIC chip
11 - interrupts: The interrupt line the device is connected to
16 compatible = "i2c-cbus-gpio";
20 interrupt-parent = <&gpio4>;
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| D | xylon,logicvc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC multi-function device
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
15 As a result, a multi-function device is exposed as parent of the display
21 - enum:
22 - xylon,logicvc-3.02.a
23 - const: syscon
24 - const: simple-mfd
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| D | mfd.txt | 1 Multi-Function Devices (MFD)
4 more than one non-unique yet varying hardware functionality.
8 - A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management
14 - A range of memory registers containing "miscellaneous system registers" also
20 - compatible : "simple-mfd" - this signifies that the operating system should
22 "simple-bus" indicates when to see subnodes as children for a simple
23 memory-mapped bus. For more complex devices, when the nexus driver has to
28 - ranges: Describes the address mapping relationship to the parent. Should set
29 the child's base address to 0, the physical address within parent's address
30 space, and the length of the address map.
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| /Documentation/devicetree/bindings/usb/ |
| D | fsl-usb.txt | 9 - compatible : Should be "fsl-usb2-mph" for multi port host USB
10 controllers, or "fsl-usb2-dr" for dual role USB controllers
11 or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
13 also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
14 - phy_type : For multi port host USB controllers, should be one of
17 - reg : Offset and length of the register set for the device
18 - port0 : boolean; if defined, indicates port0 is connected for
19 fsl-usb2-mph compatible controllers. Either this property or
20 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
22 - port1 : boolean; if defined, indicates port1 is connected for
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
10 reading descriptor address to a particular memory mapped location. The PDSPs
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
27 external link ram entries. If the address is specified as "0"
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | cpm.txt | 10 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11 - reg : A 48-byte region beginning with CPCR.
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
24 - fsl,cpm-command : This value is ORed with the opcode and command flag
27 - fsl,cpm-brg : Indicates which baud rate generator the device
32 - reg : Unless otherwise specified, the first resource represents the
36 * Multi-User RAM (MURAM)
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ad5696.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5696 and similar multi-channel DACs
10 - Michael Auchter <michael.auchter@ni.com>
13 Binding for Analog Devices AD5696 and similar multi-channel DACs
18 - adi,ad5311r
19 - adi,ad5338r
20 - adi,ad5671r
21 - adi,ad5675r
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| /Documentation/arch/s390/ |
| D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 - Pierre Morel
17 -----------------------
28 ---------------
36 - /sys/kernel/debug/s390dbf/pci_msg/sprintf
56 - /sys/bus/pci/slots/XXXXXXXX/power
64 - function_id
67 - function_handle
68 Low-level identifier used for a configured PCI function.
71 - pchid
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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| /Documentation/devicetree/bindings/media/ |
| D | st,st-hva.txt | 1 st-hva: multi-format video encoder for STMicroelectronics SoC.
4 - compatible: should be "st,st-hva".
5 - reg: HVA physical address location and length, esram address location and
7 - reg-names: names of the registers listed in registers property in the same
9 - interrupts: HVA interrupt number.
10 - clocks: from common clock binding: handle hardware IP needed clocks, the
12 See ../clock/clock-bindings.txt for details.
13 - clock-names: names of the clocks listed in clocks property in the same order.
17 compatible = "st,st-hva";
19 reg-names = "hva_registers", "hva_esram";
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| /Documentation/sound/cards/ |
| D | cmipci.rst | 2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
51 control switch in the driver "Line-In As Rear", which you can change
52 via alsamixer or somewhat else. When this switch is on, line-in jack
60 4/6 Multi-Channel Playback
61 --------------------------
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| /Documentation/devicetree/bindings/regulator/ |
| D | da9210.txt | 1 * Dialog Semiconductor DA9210 Multi-phase 12A DCDC BUCK Converter
5 - compatible: must be "dlg,da9210"
6 - reg: the i2c slave address of the regulator. It should be 0x68.
10 - interrupts: a reference to the DA9210 interrupt, if available.
21 interrupt-parent = <...>;
24 regulator-min-microvolt = <300000>;
25 regulator-max-microvolt = <1570000>;
26 regulator-min-microamp = <1600000>;
27 regulator-max-microamp = <4600000>;
28 regulator-boot-on;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | openrisc,ompic.txt | 1 Open Multi-Processor Interrupt Controller
5 - compatible : This should be "openrisc,ompic"
6 - reg : Specifies base physical address and size of the register space. The
9 - interrupt-controller : Identifies the node as an interrupt controller.
10 - #interrupt-cells : This should be set to 0 as this will not be an irq
12 - interrupts : Specifies the interrupt line to which the ompic is wired.
16 ompic: interrupt-controller@98000000 {
19 interrupt-controller;
20 #interrupt-cells = <0>;
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| /Documentation/hwmon/ |
| D | mp2888.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 -----------
20 vendor dual-loop, digital, multi-phase controller MP2888.
24 - One power rail.
25 - Programmable Multi-Phase up to 10 Phases.
26 - PWM-VID Interface
27 - One pages 0 for telemetry.
28 - Programmable pins for PMBus Address.
29 - Built-In EEPROM to Store Custom Configurations.
33 - PMBus rev 1.3 interface.
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