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/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
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Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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Daxis,artpec6-pcie.txt1 * Axis ARTPEC-6 PCIe interface
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
15 - "phy"
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Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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/Documentation/devicetree/bindings/media/
Dstih407-c8sectpfe.txt14 - compatible : Should be "stih407-c8sectpfe"
16 - reg : Address and length of register sets for each device in
17 "reg-names"
19 - reg-names : The names of the register addresses corresponding to the
21 - c8sectpfe: c8sectpfe registers
22 - c8sectpfe-ram: c8sectpfe internal sram
24 - clocks : phandle list of c8sectpfe clocks
25 - clock-names : should be "c8sectpfe"
26 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
28 - pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
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/Documentation/devicetree/bindings/eeprom/
Dat24.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
14 - $ref: /schemas/nvmem/nvmem.yaml
20 pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
22 - compatible
26 pattern: "^eeprom@[0-9a-f]{1,2}$"
36 - allOf:
37 - minItems: 1
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/Documentation/misc-devices/
Dpci-endpoint-test.rst1 .. SPDX-License-Identifier: GPL-2.0
15 #) verifying addresses programmed in BAR
18 #) raise MSI-X IRQ
23 This misc driver creates /dev/pci-endpoint-test.<num> for every
28 -----
39 Tests message signalled interrupts. The MSI-X number
43 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
56 .. [1] Documentation/PCI/endpoint/function/binding/pci-test.rst
/Documentation/devicetree/bindings/nvmem/layouts/
Donie,tlv-layout.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/onie,tlv-layout.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 infrastructure shall provide a non-volatile memory with a table whose the
17 number, hardware version, mac addresses, etc). The underlying device type
26 const: onie,tlv-layout
28 product-name:
32 part-number:
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dqe.txt16 - compatible : should be "fsl,qe";
17 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18 - reg : offset and length of the device registers.
19 - bus-frequency : the clock frequency for QUICC Engine.
20 - fsl,qe-num-riscs: define how many RISC engines the QE has.
21 - fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
26 - fsl,firmware-phandle:
27 Usage: required only if there is no fsl,qe-firmware child node
32 "fsl,qe-firmware".
35 - brg-frequency : the internal clock source frequency for baud-rate
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/Documentation/netlink/specs/
Drt_link.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 name: rt-link
4 protocol: netlink-raw
11 -
12 name: ifinfo-flags
15 -
17 -
19 -
21 -
23 -
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/Documentation/devicetree/bindings/net/
Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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/Documentation/trace/
Dkprobes.rst29 collect debugging and performance information non-disruptively. You
41 In the typical case, Kprobes-based instrumentation is packaged as
56 Kprobes -- e.g., the difference between a pre_handler and
62 -----------------------
71 associated with the kprobe, passing the handler the addresses of the
74 Next, Kprobes single-steps its copy of the probed instruction.
75 (It would be simpler to single-step the actual instruction in place,
80 After the instruction is single-stepped, Kprobes executes the
85 -----------------------
105 -------------
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/Documentation/devicetree/bindings/iommu/
Diommu.txt13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
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/Documentation/networking/dsa/
Ddsa.rst22 An Ethernet switch typically comprises multiple front-panel ports and one
27 gateways, or even top-of-rack switches. This host Ethernet controller will
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
57 - the "cpu" port is the Ethernet switch facing side of the management
61 - the "dsa" port(s) are just conduits between two or more switches, and as such
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/Documentation/i2c/
Dwriting-clients.rst19 it for non-exported symbols too. We will use the prefix ``foo_`` in this
28 routines, and should be zero-initialized except for fields with data you
29 provide. A client structure holds device-specific information like the
66 All other fields are for call-back functions which will be explained
74 structure at all. You should use this to keep device-specific data.
85 to NULL in remove() or if probe() failed anymore. The i2c-core does this
99 but many chips have some kind of register-value idea that can easily
107 if (reg < 0x10) /* byte-sized register */
109 else /* word-sized register */
115 if (reg == 0x10) /* Impossible to write - driver error! */
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/Documentation/networking/
Drepresentors.rst1 .. SPDX-License-Identifier: GPL-2.0
8 used to control internal switching on SmartNICs. For the closely-related port
9 representors on physical (multi-port) switches, see
13 ----------
15 Since the mid-2010s, network cards have started offering more complex
16 virtualisation capabilities than the legacy SR-IOV approach (with its simple
17 MAC/VLAN-based switching model) can support. This led to a desire to offload
18 software-defined networks (such as OpenVSwitch) to these NICs to specify the
23 virtual switches and IOV devices. Just as each physical port of a Linux-
41 -----------
[all …]
Drxrpc.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The RxRPC protocol driver provides a reliable two-phase transport on top of UDP
38 RxRPC is a two-layer protocol. There is a session layer which provides
44 +-------------+
46 +-------------+
48 +-------------+
50 +-------------+
52 +-------------+
60 (2) A two-phase protocol. The client transmits a blob (the request) and then
82 to use - currently only PF_INET is supported.
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/Documentation/livepatch/
Dmodule-elf-format.rst16 Formerly, livepatch required separate architecture-specific code to write
17 relocations. However, arch-specific code to write relocations already
19 code. So, instead of duplicating code and re-implementing what the module
21 loader to perform the all the arch-specific relocation work. Specifically,
26 of arch-specific code required to port livepatch to a particular
34 selected from OS-specific ranges according to the definitions from glibc.
37 -----------------------------------------------------
39 reference non-exported global symbols and non-included local symbols.
40 Relocations referencing these types of symbols cannot be left in as-is
49 approach required livepatch to supply arch-specific code in order to write
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/Documentation/usb/
Dgadget-testing.rst38 Function-specific configfs interface
39 ------------------------------------
46 The attribute is read-only.
52 ------------------------
77 Function-specific configfs interface
78 ------------------------------------
100 ------------------------
102 Configure IP addresses of the device and the host. Then:
117 Function-specific configfs interface
118 ------------------------------------
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/Documentation/admin-guide/
Dkernel-parameters.txt5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
26 If set to vendor, prefer vendor-specific driver
34 force FADT to use 32 bit addresses rather than the
35 64 bit X_* addresses. Some firmware have broken 64
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/Documentation/networking/device_drivers/ethernet/intel/
Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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