Searched full:peripherals (Results 1 – 25 of 155) sorted by relevance
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| /Documentation/devicetree/bindings/display/ |
| D | mipi-dsi-bus.txt | 5 communication between a host and up to four peripherals. This document will
13 peripherals on that bus.
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
42 Peripherals with DSI as control bus, or no control bus
45 Peripherals with the DSI bus as the primary control bus, or peripherals with
48 DSI peripherals, but individual bindings may want to define additional,
55 Some DSI peripherals respond to more than a single virtual channel. In that
64 Peripherals with a different control bus
67 There are peripherals that have I2C/SPI (or some other non-DSI bus) as the
69 path). Connections between such peripherals and a DSI host can be represented
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| /Documentation/devicetree/bindings/clock/ |
| D | amlogic,a1-peripherals-clkc.yaml | 4 $id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#
7 title: Amlogic A1 Peripherals Clock Control Unit
17 const: amlogic,a1-peripherals-clkc
60 compatible = "amlogic,a1-peripherals-clkc";
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| D | brcm,bcm2835-aux-clock.txt | 6 The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
7 area controlling clock gating to the peripherals, and providing an IRQ
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| D | lpc1850-creg-clk.txt | 8 These clocks are used by the RTC and the Event Router peripherals.
9 The 32 kHz can also be routed to other peripherals to enable low
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| D | mediatek,mt7621-sysc.yaml | 14 as well as derived clocks for the bus and the peripherals. It also
25 This node is also a reset provider for all the peripherals.
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| D | pistachio-clock.txt | 21 co-processor), audio, and several peripherals.
48 peripherals. The peripheral system clock ("periph_sys") generated by the core
75 resets for various peripherals. It also contains miscellaneous peripheral
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| /Documentation/devicetree/bindings/bus/ |
| D | fsl,spba-bus.yaml | 7 title: Shared Peripherals Bus Interface
13 A simple bus enabling access to shared peripherals.
18 determine which peripherals are available to it and the range over which
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| D | baikal,bt1-axi.yaml | 18 another: from CPU to SoC peripherals and between some SoC peripherals
20 some peripherals). In case of any protocol error, device not responding
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| D | ts-nbus.txt | 3 The NBUS is a bus used to interface with peripherals in the Technologic
20 The NBUS node can contain zero or more child nodes representing peripherals
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| D | ti,da850-mstpri.txt | 5 peripherals classified as masters.
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| /Documentation/devicetree/bindings/arm/ |
| D | primecell.yaml | 7 title: ARM Primecell Peripherals
13 ARM, Ltd. Primecell peripherals have a standard id register that can be used to
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mc-peripheral-props.yaml | 14 and there can be multiple peripherals attached to a controller. All
37 - $ref: ingenic,nemc-peripherals.yaml#
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-atr.yaml | 26 used to access the remote peripherals on the serializer's I2C bus. The
31 needed if there are no I2C addressable remote peripherals.
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| /Documentation/devicetree/bindings/gpio/ |
| D | st,stmpe-gpio.yaml | 11 bus controllers for various expanded peripherals such as GPIO, keypad,
13 peripherals connected to SPI or I2C. These bindings pertain to the
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| /Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | hi3798cv200-perictrl.yaml | 13 The Hi3798CV200 Peripheral Controller controls peripherals, queries
14 their status, and configures some functions of peripherals.
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| /Documentation/devicetree/bindings/misc/ |
| D | ge-achc.yaml | 12 A device which handles data acquisition from compatible USB based peripherals.
15 Note: This device does not expose the peripherals as USB devices.
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| D | lwn-bk4.txt | 4 peripherals.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | starfive,jh7110-sys-pinctrl.yaml | 15 Some peripherals have their I/O go through the 64 "GPIOs". This also
17 All these peripherals are connected to all 64 GPIOs such that
18 any GPIO can be set up to be controlled by any of the peripherals.
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| /Documentation/devicetree/bindings/x86/ |
| D | ce4100.txt | 4 The CE4100 SoC uses for in core peripherals the following compatible
44 This node describes the in-core peripherals. Required property:
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| /Documentation/devicetree/bindings/thermal/ |
| D | qcom,spmi-temp-alarm.yaml | 13 QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips
14 that utilize the Qualcomm SPMI implementation. These peripherals provide an
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| /Documentation/devicetree/bindings/dma/ti/ |
| D | k3-bcdma.yaml | 20 optional triggers a block copy channel can service peripherals by accessing
23 Split channels can be used to service PSI-L based peripherals.
24 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
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| /Documentation/devicetree/bindings/net/can/ |
| D | st,stm32-bxcan.yaml | 25 two CAN peripherals in dual CAN configuration. In that case they share
35 has two CAN peripherals in dual CAN configuration. In that case they
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap5-dss.txt | 56 - RFBI controlled peripherals
74 - DSI controlled peripherals
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| /Documentation/devicetree/ |
| D | overlay-notes.rst | 33 /* On chip peripherals */
35 /* peripherals that are always instantiated */
67 /* On chip peripherals */
69 /* peripherals that are always instantiated */
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| /Documentation/devicetree/bindings/mfd/ |
| D | ti-keystone-devctrl.txt | 4 the status of its peripherals. This node is intended to allow access to
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