Searched full:pipeline (Results 1 – 25 of 75) sorted by relevance
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| /Documentation/gpu/ |
| D | komeda-kms.rst | 15 architecture. A display pipeline is made up of multiple individual and
16 functional pipeline stages called components, and every component has some
17 specific capabilities that can give the flowed pipeline pixel data a
24 Layer is the first pipeline stage, which prepares the pixel data for the next
58 Final stage of display pipeline, Timing controller is not for the pixel
76 Possible D71 Pipeline usage
94 Single pipeline data flow
98 :alt: Single pipeline digraph
99 :caption: Single pipeline data flow
140 Dual pipeline with Slave enabled
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| D | automated_testing.rst | 34 some variables that can be modified to change the behavior of the pipeline:
89 3. Next time you push to this repository, you will see a CI pipeline being
92 4. The various jobs will be run and when the pipeline is finished, all jobs
134 If the pipeline is not in a merge request and a branch with the same name
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| /Documentation/gpu/amdgpu/display/ |
| D | dcn-overview.rst | 6 (DCN) works, we need to start with an overview of the hardware pipeline. Below
53 pipeline is connected to the Scalable Data Port (SDP) via DCHUB; you can see
86 Display pipeline can be broken down into two components that are usually
127 AMD Hardware Pipeline
130 When discussing graphics on Linux, the **pipeline** term can sometimes be
132 when we say **pipeline**. In the DCN driver, we use the term **hardware
133 pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
135 core treats DCN blocks as individual resources, meaning we can build a pipeline
136 by taking resources for all individual hardware blocks to compose one pipeline.
139 arbitrarily assigned as needed. We have this pipeline concept for trying to
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| /Documentation/devicetree/bindings/arm/mstar/ |
| D | mstar,l3bridge.yaml | 14 MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
16 devices are allowed to run the pipeline must be flushed to ensure
23 are and install a barrier that triggers the required pipeline flush.
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| /Documentation/devicetree/bindings/display/ |
| D | arm,komeda.yaml | 15 to a 4K resolution each. Each pipeline can be composed of up to four
59 '^pipeline@[01]$':
90 - pipeline@0
107 dp0_pipe0: pipeline@0 {
119 dp0_pipe1: pipeline@1 {
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| D | allwinner,sun4i-a10-display-engine.yaml | 7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
35 For a two pipeline system such as the one depicted above, the lines
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| D | simple-framebuffer.yaml | 129 allwinner,pipeline:
130 description: Pipeline used by the framebuffer on Allwinner SoCs
145 amlogic,pipeline:
146 description: Pipeline used by the framebuffer on Amlogic SoCs
172 - allwinner,pipeline
182 - amlogic,pipeline
200 allwinner,pipeline = "de_be0-lcd0";
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
10 node of the VIPP represents as a top level node of the pipeline and defines
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| D | video.txt | 6 creating a video pipeline.
12 The whole pipeline is represented by an AMBA bus child node in the device
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| /Documentation/userspace-api/media/v4l/ |
| D | dev-subdev.rst | 97 responsible for configuring every block in the video pipeline according
98 to the requested format at the pipeline input and/or output.
101 image sizes at the output of a pipeline can be achieved using different
103 :ref:`pipeline-scaling`, where image scaling can be performed on both
109 .. kernel-figure:: pipeline.dot
110 :alt: pipeline.dot
115 High quality and high speed pipeline configuration
121 Depending on the use case (quality vs. speed), the pipeline must be
123 every point in the pipeline explicitly.
133 whole pipeline and making sure that connected pads have compatible
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| D | metafmt-intel-ipu3.rst | 43 Pipeline parameters
46 The pipeline parameters are passed to the "ipu3-imgu [01] parameters" metadata
50 Both 3A statistics and pipeline parameters described here are closely tied to
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| D | pixfmt-compressed.rst | 66 H264 pipeline with the :ref:`stateless_decoder`.
120 MPEG-2 pipeline with the :ref:`stateless_decoder`.
164 VP8 pipeline with the :ref:`stateless_decoder`.
186 VP9 pipeline with the :ref:`stateless_decoder`.
211 HEVC pipeline (using the :ref:`mem2mem` and :ref:`media-request-api`).
267 pipeline with the :ref:`stateless_decoder`. Metadata associated with the
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| D | vidioc-streamon.rst | 101 pipeline configuration is invalid.
104 The driver implements Media Controller interface and the pipeline
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| /Documentation/admin-guide/media/ |
| D | qcom_camss.rst | 38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
40 interface feeds the input data to the image processing pipeline. The image
41 processing pipeline contains also a scale and crop module at the end. Three
43 pipeline. The VFE also contains the AXI bus interface which writes the output
137 The media controller pipeline graph is as follows (with connected two / three
146 Media pipeline graph 8x16
152 Media pipeline graph 8x96
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| D | vimc.rst | 18 :alt: Diagram of the default media pipeline topology
21 Media pipeline graph on vimc
28 configuration on each linked subdevice to stream frames through the pipeline.
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| D | imx.rst | 123 :alt: Diagram of the i.MX6Q SabreSD media pipeline topology
126 Media pipeline graph on i.MX6Q SabreSD
129 :alt: Diagram of the i.MX6Q SabreAuto media pipeline topology
132 Media pipeline graph on i.MX6Q SabreAuto
286 or mem2mem device node. With this pipeline, the VDIC can also operate
341 ipuX_vdic is included in the pipeline (ipuX_ic_prp is receiving from
378 This pipeline uses the preprocess encode entity to route frames directly
387 This pipeline routes frames from the CSI direct pad to the VDIC entity to
400 in the current pipeline, so controls can be accessed either directly
449 # Configure pads for OV5642 pipeline
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| D | fimc.rst | 31 - dynamic pipeline re-configuration at runtime (re-attachment of any FIMC
90 In order to enable more precise camera pipeline control through the sub-device
94 In typical use case there could be a following capture pipeline configuration:
102 devices belonging to the pipeline is done at the video node driver.
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| D | imx7.rst | 68 inherit controls from the active entities in the current pipeline, so controls
77 CSI-2 receiver. The following example configures a video capture pipeline with
88 # Configure pads for pipeline
162 The following example configures a video capture pipeline with an output
171 # Configure pads for pipeline
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| /Documentation/driver-api/media/ |
| D | mc-core.rst | 24 in a System-on-Chip image processing pipeline), DMA channels or physical
223 A media pipeline is a set of media streams which are interdependent. This
226 due to the software design. Most commonly a media pipeline consists of a single
229 When starting streaming, drivers must notify all entities in the pipeline to
233 The function will mark all the pads which are part of the pipeline as streaming.
236 stored in every pad in the pipeline. Drivers should embed the struct
237 media_pipeline in higher-level pipeline structures and can then access the
238 pipeline through the struct media_pad pipe field.
241 The pipeline pointer must be identical for all nested calls to the function.
268 for any entity which has sink pads in the pipeline. The
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| D | camera-sensor.rst | 55 processing pipeline as one or more sub-devices with different cropping and
68 format set on a source pad at the end of the device's internal pipeline.
105 device's internal processing pipeline.
107 The first entity in the linear pipeline is the pixel array. The pixel array may
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| /Documentation/networking/devlink/ |
| D | devlink-dpipe.rst | 16 Linux kernel may differ from the hardware implementation. The pipeline debug
18 pipeline in a generic way.
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
77 The hardware pipeline is not port specific, but rather describes the whole
163 the pipeline. The table sizes in the following examples are not real
175 pipeline which resolves the MAC address. The next stage can be either local
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| /Documentation/devicetree/bindings/media/ |
| D | fsl,imx6ull-pxp.yaml | 8 title: Freescale Pixel Pipeline
15 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
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| /Documentation/devicetree/bindings/arc/ |
| D | archs-pct.txt | 3 The ARC HS can be configured with a pipeline performance monitor for counting
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| D | pct.txt | 3 The ARC700 can be configured with a pipeline performance monitor for counting
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | megachips-stdpxxxx-ge-b850v3-fw.txt | 5 The video processing pipeline on the second output on the GE B850v3:
15 The hardware do not provide control over the video processing pipeline, as the
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