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/Documentation/devicetree/bindings/power/
Drockchip,power-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Power Domains
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 Rockchip processors include support for multiple power domains
16 application scenarios to save power.
18 Power domains contained within power-controller node are
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Dpower-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rjw@rjwysocki.net>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
16 used for power gating of selected IP blocks for power saving by reduced leakage
24 \#power-domain-cells property in the PM domain provider node.
28 pattern: "^(power-controller|power-domain)([@-].*)?$"
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Dbrcm,bcm63xx-power.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/brcm,bcm63xx-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM63xx power domain driver
10 - Álvaro Fernández Rojas <noltari@gmail.com>
13 BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller
14 to enable/disable certain components in order to save power.
19 - enum:
20 - brcm,bcm6318-power-controller
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Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Power Domains Controller
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
14 Mediatek processors include support for multiple power domains which can be
15 powered up/down by software based on different application scenes to save power.
17 IP cores belonging to a power domain should contain a 'power-domains'
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Dfsl,imx-gpcv2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX General Power Controller v2
10 - Andrey Smirnov <andrew.smirnov@gmail.com>
13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
14 Control (PGC) for various power domains.
16 Power domains contained within GPC node are generic power domain
18 Documentation/devicetree/bindings/power/power-domain.yaml, which are
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Dfsl,imx-gpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX General Power Controller
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 The i.MX6 General Power Control (GPC) block contains DVFS load tracking
14 counters and Power Gating Control (PGC).
16 The power domains are generic power domain providers as documented in
17 Documentation/devicetree/bindings/power/power-domain.yaml. They are
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Dpower_domain.txt4 used for power gating of selected IP blocks for power saving by reduced leakage
12 #power-domain-cells property in the PM domain provider node.
16 See power-domain.yaml.
21 - power-domains : A list of PM domain specifiers, as defined by bindings of
22 the power controller that is the PM domain provider.
25 - power-domain-names : A list of power domain name strings sorted in the same
26 order as the power-domains property. Consumers drivers will use
27 power-domain-names to match power domains with power-domains
32 leaky-device@12350000 {
33 compatible = "foo,i-leak-current";
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Damlogic,meson-gx-pwrc.txt1 Amlogic Meson Power Controller (deprecated)
4 The Amlogic Meson SoCs embeds an internal Power domain controller.
6 VPU Power Domain
7 ----------------
9 The Video Processing Unit power domain is controlled by this power controller,
10 but the domain requires some external resources to meet the correct power
12 The bindings must respect the power domain bindings as described in the file
13 power-domain.yaml
16 ---------------------
19 - compatible: should be one of the following :
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Dallwinner,sun20i-d1-ppu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner SoCs PPU power domain controller
10 - Samuel Holland <samuel@sholland.org>
13 D1 and related SoCs contain a power domain controller for the CPUs, GPU, and
14 video-related hardware.
19 - allwinner,sun20i-d1-ppu
31 '#power-domain-cells':
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/Documentation/devicetree/bindings/arm/apple/
Dapple,pmgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC Power Manager (PMGR)
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs include PMGR blocks responsible for power management,
14 which can control various clocks, resets, power states, and
16 with sub-nodes representing individual features.
20 pattern: "^power-management@[0-9a-f]+$"
24 - enum:
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/Documentation/devicetree/bindings/soc/ti/
Dsci-pm-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI generic power domain
10 - Nishanth Menon <nm@ti.com>
13 - $ref: /schemas/power/power-domain.yaml#
16 Some TI SoCs contain a system controller (like the Power Management Micro
17 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
19 between the host processor running an OS and the system controller happens
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/Documentation/devicetree/bindings/mfd/
Dmediatek,mt8195-scpsys.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
14 power management tasks. The tasks include MTCMOS power
20 - enum:
21 - mediatek,mt8167-scpsys
22 - mediatek,mt8173-scpsys
23 - mediatek,mt8183-scpsys
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Dmax77620.txt1 MAX77620 Power management IC from Maxim Semiconductor.
4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
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Dene-kb930.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/ene-kb930.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ENE KB930 Embedded Controller
10 This binding describes the ENE KB930 Embedded Controller attached to an
14 - Dmitry Osipenko <digetx@gmail.com>
16 $ref: /schemas/power/supply/power-supply.yaml
21 - enum:
22 - acer,a500-iconia-ec # Acer A500 Iconia tablet device
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/Documentation/devicetree/bindings/nvme/
Dapple,nvme-ans.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvme/apple,nvme-ans.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple ANS NVM Express host controller
10 - Sven Peter <sven@svenpeter.dev>
15 - enum:
16 - apple,t8103-nvme-ans2
17 - apple,t8112-nvme-ans2
18 - apple,t6000-nvme-ans2
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/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,vcodecsys.txt1 Mediatek vcodecsys controller
4 The Mediatek vcodecsys controller provides various clocks to the system.
8 - compatible: Should be one of:
9 - "mediatek,mt6765-vcodecsys", "syscon"
10 - #clock-cells: Must be 1
12 The vcodecsys controller uses the common clk binding from
13 Documentation/devicetree/bindings/clock/clock-bindings.txt
14 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
16 The vcodecsys controller also uses the common power domain from
18 The available power domains are defined in dt-bindings/power/mt*-power.h.
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Dmediatek,mipi0a.txt1 Mediatek mipi0a (mipi_rx_ana_csi0a) controller
4 The Mediatek mipi0a controller provides various clocks
9 - compatible: Should be one of:
10 - "mediatek,mt6765-mipi0a", "syscon"
11 - #clock-cells: Must be 1
13 The mipi0a controller uses the common clk binding from
14 Documentation/devicetree/bindings/clock/clock-bindings.txt
15 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
17 The mipi0a controller also uses the common power domain from
19 The available power domains are defined in dt-bindings/power/mt*-power.h.
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/Documentation/devicetree/bindings/power/reset/
Dgemini-poweroff.txt1 * Device-Tree bindings for Cortina Systems Gemini Poweroff
4 deals with different ways to power the system down.
7 - compatible: should be "cortina,gemini-power-controller"
8 - reg: should contain the physical memory base and size
9 - interrupts: should contain the power management interrupt
13 power-controller@4b000000 {
14 compatible = "cortina,gemini-power-controller";
/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,mu-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
10 - Frank Li <Frank.Li@nxp.com>
23 registers (Processor A-side, Processor B-side).
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
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/Documentation/driver-api/thermal/
Dpower_allocator.rst2 Power allocator governor tunables
6 -----------
19 PID Controller
20 --------------
22 The power allocator governor implements a
23 Proportional-Integral-Derivative controller (PID controller) with
24 temperature as the control input and power as the controlled output:
29 - e = desired_temperature - current_temperature
30 - err_integral is the sum of previous errors
31 - diff_err = e - previous_error
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/Documentation/devicetree/bindings/usb/
Dnvidia,tegra194-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra194-xusb
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Dnvidia,tegra186-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra186-xusb
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Dnvidia,tegra210-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra210-xusb
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/Documentation/devicetree/bindings/soc/renesas/
Drenesas,rzv2m-pwc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/renesas/renesas,rzv2m-pwc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M External Power Sequence Controller (PWC)
12 - external power supply on/off sequence generation
13 - on/off signal generation for the LPDDR4 core power supply (LPVDD)
14 - key input signals processing
15 - general-purpose output pins
18 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
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/Documentation/ABI/testing/
Dsysfs-class-scsi_host6 SCU controller. The Intel(R) C600 Series Chipset SATA/SAS
7 Storage Control Unit embeds up to two 4-port controllers in
10 with the first controller, but this association is not
12 the controller index: '0' for the first controller,
24 '1' indicates the feature is enabled, and the controller may
26 means the feature is disabled and the controller may not use
28 controller wide, affecting all configured logical drives on the
29 controller. This file is readable and writable.
34 Contact: linux-ide@vger.kernel.org
37 (interface) power management.
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