Searched full:reg (Results 1 – 25 of 3187) sorted by relevance
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-bcm6358.txt | 13 - reg : BCM6358 LED controller address and size.
24 - reg : LED pin number (only LEDs 0 to 31 are valid).
41 reg = <0xfffe00d0 0x8>;
44 reg = <0>;
49 reg = <2>;
54 reg = <3>;
59 reg = <4>;
70 reg = <0x100000d0 0x8>;
75 reg = <0>;
80 reg = <1>;
[all …]
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| D | leds-bcm6328.yaml | 40 reg:
76 reg:
112 - reg
117 - reg
130 reg = <0x10000800 0x24>;
133 reg = <2>;
139 reg = <3>;
145 reg = <4>;
152 reg = <17>;
157 reg = <18>;
[all …]
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| /Documentation/devicetree/bindings/mux/ |
| D | reg-mux.yaml | 4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
19 - reg-mux # parent device of mux controller is not syscon device
22 reg: true
27 mux-reg-masks:
39 - mux-reg-masks
51 compatible = "reg-mux";
53 mux-reg-masks =
54 <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
55 <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
66 reg = <0x0>;
[all …]
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| /Documentation/devicetree/bindings/nvmem/ |
| D | socionext,uniphier-efuse.yaml | 20 reg:
25 - reg
33 reg = <0x100 0x28>;
38 reg = <0x200 0x68>;
44 reg = <0x54 1>;
48 reg = <0x55 1>;
52 reg = <0x58 1>;
56 reg = <0x59 1>;
60 reg = <0x54 1>;
64 reg = <0x55 1>;
[all …]
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| D | sunplus,sp7021-ocotp.yaml | 20 reg:
23 reg-names:
49 - reg
50 - reg-names
59 reg = <0x9c00af00 0x34>, <0x9c00af80 0x58>;
60 reg-names = "hb_gpio", "otprx";
66 reg = <0x14 0x3>;
69 reg = <0x18 0x2>;
72 reg = <0x34 0x6>;
75 reg = <0x3a 0x6>;
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt8195-clock.yaml | 52 reg:
60 - reg
68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
[all …]
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| D | mediatek,mt8192-clock.yaml | 40 reg:
48 - reg
56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-ep9301.yaml | 26 reg:
33 reg-names:
60 - reg
70 reg = <0x80840000 0x04>,
73 reg-names = "data", "dir", "intr";
83 reg = <0x80840004 0x04>,
86 reg-names = "data", "dir", "intr";
96 reg = <0x80840008 0x04>,
98 reg-names = "data", "dir";
105 reg = <0x8084000c 0x04>,
[all …]
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mediatek,mt7530.yaml | 43 The driver looks up the reg on the ethernet-phy node, which the phy-handle
47 compatible string and the reg must be 1. So, for now, only gmac1 of a
95 reg:
163 reg:
173 reg:
180 - reg
193 reg:
219 reg:
306 reg = <0x1f>;
318 reg = <0>;
[all …]
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| D | qca8k.yaml | 38 reg:
68 With the legacy mapping the reg corresponding to the internal
69 mdio is the switch reg with an offset of -1.
115 - reg
129 reg = <0>;
133 reg = <1>;
137 reg = <2>;
141 reg = <3>;
145 reg = <4>;
151 reg = <0x10>;
[all …]
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| D | microchip,lan937x.yaml | 24 reg:
63 - reg
87 reg = <0>;
95 reg = <0>;
102 reg = <1>;
109 reg = <2>;
116 reg = <3>;
123 reg = <4>;
136 reg = <5>;
149 reg = <6>;
[all …]
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| D | lantiq-gswip.txt | 12 - reg : memory range of the GSWIP core registers
39 - reg : Offset of the GPHY firmware register in the RCU
52 reg = < 0xe108000 0x3100 /* switch */
63 reg = <0>;
70 reg = <1>;
77 reg = <2>;
84 reg = <4>;
91 reg = <5>;
98 reg = <0x6>;
107 reg = <0>;
[all …]
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| D | hirschmann,hellcreek.yaml | 28 reg:
34 reg-names:
54 reg:
64 - reg
72 - reg
73 - reg-names
83 reg = <0xff240000 0x1000>,
85 reg-names = "tsn", "ptp";
93 reg = <0>;
104 reg = <2>;
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 17 - reg : shall be the physical PLL register address for the pll clock.
27 - reg : shall be the physical register address for the pmd clock.
36 - reg : shall be a list of address and length pairs describing the CSR
39 - reg-names : shall be a string list describing the reg resource. This
40 may include "csr-reg" and/or "div-reg". If this property
41 is not present, the reg property is assumed to describe
42 only "csr-reg".
67 reg = <0x0 0x17000100 0x0 0x1000>;
76 reg = <0x0 0x7e200200 0x0 0x10>;
85 reg = <0x0 0x17000120 0x0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 6 - reg: Physical base address of the IP registers and length of memory mapped region.
14 - reg: Physical base address of the IP registers and length of memory mapped region.
32 - reg: Physical base address of the IP registers and length of memory mapped region.
48 - reg: Physical base address of the IP registers and length of memory mapped region.
49 - reg-names: names of the mapped memory regions listed in regs property in
60 - reg: Physical base address of the IP registers and length of memory mapped region.
61 - reg-names: names of the mapped memory regions listed in regs property in
76 - reg: Physical base address of the IP registers and length of memory mapped region.
77 - reg-names: names of the mapped memory regions listed in regs property in
89 - reg: Physical base address of the IP registers and length of memory mapped region.
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | brcm,amac.yaml | 22 reg:
24 reg-names:
35 reg:
38 reg-names:
50 reg:
52 reg-names:
65 reg:
69 reg-names:
84 reg = <0x18022000 0x1000>,
86 reg-names = "amac_base", "idm_base";
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| D | mdio-mux-gpio.yaml | 50 reg = <2>;
55 reg = <1>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
64 reg = <2>;
65 marvell,reg-init = <3 0x10 0 0x5777>,
73 reg = <3>;
74 marvell,reg-init = <3 0x10 0 0x5777>,
82 reg = <4>;
83 marvell,reg-init = <3 0x10 0 0x5777>,
93 reg = <3>;
[all …]
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| /Documentation/devicetree/bindings/perf/ |
| D | apm-xgene-pmu.txt | 19 - reg : First resource shall be the CPU bus PMU resource.
24 - reg : First resource shall be the L3C PMU resource.
28 - reg : First resource shall be the IOB PMU resource.
32 - reg : First resource shall be the MCB PMU resource.
37 - reg : First resource shall be the MC PMU resource.
43 reg = <0x0 0x7e200000 0x0 0x1000>;
48 reg = <0x0 0x7e700000 0x0 0x1000>;
53 reg = <0x0 0x7e720000 0x0 0x1000>;
64 reg = <0x0 0x78810000 0x0 0x1000>;
69 reg = <0x0 0x7e610000 0x0 0x1000>;
[all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | renesas,rzg2l-adc.yaml | 27 reg:
62 - reg
78 reg:
83 - reg
98 reg:
105 reg:
118 reg = <0x10059000 0x400>;
132 reg = <0>;
135 reg = <1>;
138 reg = <2>;
[all …]
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| D | ti,tsc2046.yaml | 20 reg:
40 - reg
48 reg:
59 - reg
77 reg = <0>;
86 reg = <0>;
89 reg = <1>;
94 reg = <2>;
97 reg = <3>;
102 reg = <4>;
[all …]
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| D | adi,ad7292.yaml | 24 reg:
41 - reg
52 reg:
62 - reg
79 reg = <0>;
88 reg = <0>;
92 reg = <2>;
95 reg = <3>;
98 reg = <4>;
101 reg = <5>;
[all …]
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,pru-rproc.yaml | 52 reg:
58 reg-names:
99 - reg
100 - reg-names
116 reg = <0x0 0x80000>;
122 reg = <0x0 0x2000>,
125 reg-names = "dram0", "dram1", "shrdram2";
130 reg = <0x34000 0x2000>,
133 reg-names = "iram", "control", "debug";
139 reg = <0x38000 0x2000>,
[all …]
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | ppc440spe-adma.txt | 16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
23 reg = <0x00000004 0x00100000 0x100>;
24 dcr-reg = <0x060 0x020>;
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
47 reg = <0x00000004 0x00100100 0x100>;
48 dcr-reg = <0x060 0x020>;
65 - reg : <registers mapping>
72 reg = <0x00000004 0x00200000 0x400>;
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | brcm,sata-phy.yaml | 32 reg:
36 reg-names:
55 reg:
93 - reg
104 reg:
107 reg-names:
111 reg:
114 reg-names:
121 - reg
122 - reg-names
[all …]
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | megachips-stdpxxxx-ge-b850v3-fw.txt | 21 - reg : I2C bus address
24 - ports : One input port(reg = <0>) and one output port(reg = <1>)
28 - reg : I2C bus address
29 - ports : One input port(reg = <0>) and one output port(reg = <1>)
41 reg = <0x73>;
51 reg = <0>;
57 reg = <1>;
70 reg = <0x72>;
77 reg = <0>;
84 reg = <1>;
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