Searched full:reset (Results 1 – 25 of 1408) sorted by relevance
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| /Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
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| D | socionext,uniphier-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
7 title: UniPhier reset controller
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
19 - socionext,uniphier-sld8-reset
20 - socionext,uniphier-pro5-reset
21 - socionext,uniphier-pxs2-reset
22 - socionext,uniphier-ld6b-reset
23 - socionext,uniphier-ld11-reset
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| D | reset.txt | 1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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| D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
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| D | xlnx,zynqmp-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
7 title: Zynq UltraScale+ MPSoC and Versal reset
15 The PS reset subsystem is responsible for handling the external reset
16 input to the device and that all internal reset requirements are met
19 Please also refer to reset.txt in this directory for common reset
20 controller binding usage. Device nodes that need access to reset
21 lines should specify them as a reset phandle in their corresponding
22 node as specified in reset.txt.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
25 <dt-bindings/reset/xlnx-zynqmp-resets.h>
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| D | socionext,uniphier-glue-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
25 - socionext,uniphier-pxs3-usb3-reset
26 - socionext,uniphier-nx1-usb3-reset
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| D | snps,hsdk-reset.txt | 1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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| D | amlogic,meson-reset.yaml | 5 $id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
8 title: Amlogic Meson SoC Reset Controller
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
20 - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
25 "#reset-cells":
31 - "#reset-cells"
37 reset-controller@c884404 {
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| D | brcm,brcmstb-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#
7 title: Broadcom STB SW_INIT-style reset controller
10 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
12 reset lines.
14 Please also refer to reset.txt in this directory for common reset
22 const: brcm,brcmstb-reset
27 "#reset-cells":
33 - "#reset-cells"
39 reset: reset-controller@8404318 {
40 compatible = "brcm,brcmstb-reset";
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| D | img,pistachio-reset.txt | 1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
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| D | fsl,imx7-src.yaml | 4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
7 title: Freescale i.MX7 System Reset Controller
13 The system reset controller can be used to reset various set of
14 peripherals. Device nodes that need access to reset lines should
15 specify them as a reset phandle in their corresponding node as
16 specified in reset.txt.
18 For list of all valid reset indices see
19 <dt-bindings/reset/imx7-reset.h> for i.MX7,
20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
21 <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
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| D | allwinner,sun6i-a31-clock-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml#
7 title: Allwinner A31 Peripheral Reset Controller
20 - allwinner,sun6i-a31-ahb1-reset
21 - allwinner,sun6i-a31-clock-reset
31 "#reset-cells":
34 This additional argument passed to that reset controller is the
35 offset of the bit controlling this particular reset line in the
40 - allwinner,sun6i-a31-ahb1-reset
41 - allwinner,sun6i-a31-clock-reset
47 - "#reset-cells"
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| D | intel,rcu-gw.yaml | 4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
7 title: System Reset Controller on Intel Gateway SoCs
19 description: Reset controller registers.
22 intel,global-reset:
23 description: Global reset register offset and bit offset.
31 "#reset-cells":
35 First cell is reset request register offset.
36 Second cell is bit offset in reset request register.
37 Third cell is bit offset in reset status register.
38 For LGM SoC, reset cell count is 2 as bit offset in
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| D | nuvoton,npcm750-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
7 title: Nuvoton NPCM Reset controller
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
28 nuvoton,sw-reset-number:
33 Contains the software reset number to restart the SoC.
34 If not specified, software reset is disabled.
39 - '#reset-cells'
46 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
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| D | microchip,rst.yaml | 4 $id: http://devicetree.org/schemas/reset/microchip,rst.yaml#
7 title: Microchip Sparx5 Switch Reset Controller
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
25 - microchip,lan966x-switch-reset
35 "#reset-cells":
40 description: syscon used to access CPU reset
46 - "#reset-cells"
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| D | ti,tps380x-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/ti,tps380x-reset.yaml#
7 title: TI TPS380x reset controller
15 RESET signal if the voltage drops below a preset threshold or upon a manual
16 reset input (MR). The RESET output remains asserted for the factory
18 manual reset input is released.
27 reset-gpios:
31 "#reset-cells":
36 - reset-gpios
37 - "#reset-cells"
44 reset: reset-controller {
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| D | snps,axs10x-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml#
7 title: AXS10x reset controller
14 to control reset signals of selected peripherals. For example DW GMAC, etc...
16 represents up-to 32 reset lines.
22 const: snps,axs10x-reset
27 '#reset-cells':
33 - '#reset-cells'
39 reset: reset-controller@11220 {
40 compatible = "snps,axs10x-reset";
41 #reset-cells = <1>;
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| D | lantiq,reset.yaml | 4 $id: http://devicetree.org/schemas/reset/lantiq,reset.yaml#
7 title: Lantiq XWAY SoC RCU reset controller
13 This binding describes a reset-controller found on the RCU module on Lantiq
19 - lantiq,danube-reset
20 - lantiq,xrx200-reset
25 Offset of the reset set register
26 Offset of the reset status register
29 '#reset-cells':
31 The first cell takes the reset set bit and the second cell takes the
38 - '#reset-cells'
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| D | hisilicon,hi3660-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
7 title: Hisilicon System Reset Controller
13 Please also refer to reset.txt in this directory for common reset
15 The reset controller registers are part of the system-ctl block on
22 - const: hisilicon,hi3660-reset
24 - const: hisilicon,hi3670-reset
25 - const: hisilicon,hi3660-reset
29 description: phandle of the reset's syscon, use hisilicon,rst-syscon instead
33 description: phandle of the reset's syscon.
36 '#reset-cells':
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| D | snps,dw-reset.txt | 1 Synopsys DesignWare Reset controller
4 Please also refer to reset.txt in this directory for common reset
10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
16 - #reset-cells: must be 1.
20 dw_rst_1: reset-controller@0000 {
21 compatible = "snps,dw-high-reset";
23 #reset-cells = <1>;
26 dw_rst_2: reset-controller@1000 {
27 compatible = "snps,dw-low-reset";
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| D | qca,ar7100-reset.yaml | 5 $id: http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#
8 title: Qualcomm Atheros AR7xxx/AR9XXX reset controller
17 - qca,ar9132-reset
18 - qca,ar9331-reset
19 - const: qca,ar7100-reset
24 "#reset-cells":
30 - "#reset-cells"
36 reset-controller@1806001c {
37 compatible = "qca,ar9132-reset", "qca,ar7100-reset";
39 #reset-cells = <1>;
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| D | nuvoton,ma35d1-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml#
7 title: Nuvoton MA35D1 Reset Controller
14 The system reset controller can be used to reset various peripheral
20 - const: nuvoton,ma35d1-reset
25 '#reset-cells':
31 - '#reset-cells'
36 # system reset controller node:
40 compatible = "nuvoton,ma35d1-reset";
42 #reset-cells = <1>;
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| /Documentation/driver-api/ |
| D | reset.rst | 4 Reset controller API
10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
21 While some reset controller hardware units also implement system restart
22 functionality, restart handlers are out of scope for the reset controller API.
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| /Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-intel-pmc | 7 reset bits. The bits are used during an Intel platform
8 manufacturing process to indicate that consequent reset
9 of the platform is a "global reset". This type of reset
13 Display global reset setting bits for PMC.
15 * bit 31 - global reset is locked
16 * bit 20 - global reset is set
19 a platform "global reset" upon consequent platform reset,
21 The "global reset bit" should be locked on a production
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