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/drivers/pci/controller/
Dpcie-rockchip.c3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
25 #include "pcie-rockchip.h"
27 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) in rockchip_pcie_parse_dt() argument
29 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
35 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
39 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); in rockchip_pcie_parse_dt()
40 if (IS_ERR(rockchip->reg_base)) in rockchip_pcie_parse_dt()
41 return PTR_ERR(rockchip->reg_base); in rockchip_pcie_parse_dt()
43 rockchip->mem_res = in rockchip_pcie_parse_dt()
[all …]
Dpcie-rockchip-host.c3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
37 #include "pcie-rockchip.h"
39 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) in rockchip_pcie_enable_bw_int() argument
43 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); in rockchip_pcie_enable_bw_int()
45 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); in rockchip_pcie_enable_bw_int()
48 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) in rockchip_pcie_clr_bw_int() argument
52 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); in rockchip_pcie_clr_bw_int()
54 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); in rockchip_pcie_clr_bw_int()
57 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip) in rockchip_pcie_update_txcredit_mui() argument
[all …]
Dpcie-rockchip-ep.c3 * Rockchip AXI PCIe endpoint controller driver
5 * Copyright (c) 2018 Rockchip, Inc.
20 #include "pcie-rockchip.h"
24 * @rockchip: Rockchip PCIe controller
41 struct rockchip_pcie rockchip; member
53 static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, in rockchip_pcie_clear_ep_ob_atu() argument
56 rockchip_pcie_write(rockchip, 0, in rockchip_pcie_clear_ep_ob_atu()
58 rockchip_pcie_write(rockchip, 0, in rockchip_pcie_clear_ep_ob_atu()
60 rockchip_pcie_write(rockchip, 0, in rockchip_pcie_clear_ep_ob_atu()
62 rockchip_pcie_write(rockchip, 0, in rockchip_pcie_clear_ep_ob_atu()
[all …]
Dpcie-rockchip.h3 * Rockchip AXI PCIe controller driver
5 * Copyright (c) 2018 Rockchip, Inc.
323 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) in rockchip_pcie_read() argument
325 return readl(rockchip->apb_base + reg); in rockchip_pcie_read()
328 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, in rockchip_pcie_write() argument
331 writel(val, rockchip->apb_base + reg); in rockchip_pcie_write()
334 int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip);
335 int rockchip_pcie_init_port(struct rockchip_pcie *rockchip);
336 int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
337 void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
[all …]
/drivers/pci/controller/dwc/
Dpcie-dw-rockchip.c3 * PCIe host controller driver for Rockchip SoCs.
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
63 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, in rockchip_pcie_readl_apb() argument
66 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
69 static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, in rockchip_pcie_writel_apb() argument
72 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
78 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); in rockchip_pcie_legacy_int_handler() local
83 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY); in rockchip_pcie_legacy_int_handler()
86 generic_handle_domain_irq(rockchip->irq_domain, hwirq); in rockchip_pcie_legacy_int_handler()
125 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) in rockchip_pcie_init_irq_domain() argument
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/drivers/phy/rockchip/
DKconfig3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
[all …]
DMakefile2 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
3 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
4 obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
5 obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
6 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
7 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
8 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
9 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
10 obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
11 obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
[all …]
Dphy-rockchip-snps-pcie3.c3 * Rockchip PCIE3.0 phy driver
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
248 priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); in rockchip_p3phy_probe()
250 dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); in rockchip_p3phy_probe()
254 if (of_device_is_compatible(np, "rockchip,rk3588-pcie3-phy")) { in rockchip_p3phy_probe()
257 "rockchip,pipe-grf"); in rockchip_p3phy_probe()
259 dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); in rockchip_p3phy_probe()
303 { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
304 { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
312 .name = "rockchip-snps-pcie3-phy",
[all …]
Dphy-rockchip-usb.c3 * Rockchip usb PHY driver
6 * Copyright (C) 2014 ROCKCHIP, Inc.
484 dev->of_node, "rockchip,grf"); in rockchip_usb_phy_probe()
486 dev_err(&pdev->dev, "Missing rockchip,grf property\n"); in rockchip_usb_phy_probe()
503 { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
504 { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
505 { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
514 .name = "rockchip-usb-phy",
553 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_init_usb_uart()
555 pr_err("%s: Missing rockchip,grf property, %lu\n", in rockchip_init_usb_uart()
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/drivers/gpu/drm/rockchip/
DKconfig3 tristate "DRM Support for Rockchip"
16 Choose this option if you have a Rockchip soc chipset.
25 bool "Rockchip VOP driver"
32 bool "Rockchip VOP2 driver"
38 bool "Rockchip specific extensions for Analogix DP driver"
43 This selects support for Rockchip SoC specific extensions
48 bool "Rockchip cdn DP"
53 This selects support for Rockchip SoC specific extensions
59 bool "Rockchip specific extensions for Synopsys DW HDMI"
61 This selects support for Rockchip SoC specific extensions
[all …]
Drockchip_drm_drv.c3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
39 #define DRIVER_NAME "rockchip"
40 #define DRIVER_DESC "RockChip Soc DRM"
296 * Check if a vop endpoint is leading to a rockchip subdriver or bridge.
300 * @ep: endpoint of a rockchip vop
329 * All rockchip subdrivers have probed at this point, so in rockchip_drm_endpoint_is_subdriver()
467 { .compatible = "rockchip,display-subsystem", },
477 .name = "rockchip-drm",
541 MODULE_DESCRIPTION("ROCKCHIP DRM Driver");
/drivers/clk/rockchip/
DKconfig2 # common clock support for ROCKCHIP SoC family.
5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
20 bool "Rockchip RV110x clock controller support"
27 bool "Rockchip RV1126 clock controller support"
34 bool "Rockchip RK3036 clock controller support"
41 bool "Rockchip RK312x clock controller support"
48 bool "Rockchip RK3188 clock controller support"
55 bool "Rockchip RK322x clock controller support"
[all …]
DMakefile3 # Rockchip Clock specific Makefile
6 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
8 clk-rockchip-y += clk.o
9 clk-rockchip-y += clk-pll.o
10 clk-rockchip-y += clk-cpu.o
11 clk-rockchip-y += clk-half-divider.o
12 clk-rockchip-y += clk-inverter.o
13 clk-rockchip-y += clk-mmc-phase.o
14 clk-rockchip-y += clk-muxgrf.o
15 clk-rockchip-y += clk-ddr.o
[all …]
/drivers/nvmem/
Drockchip-efuse.c3 * Rockchip eFuse Driver
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
207 .name = "rockchip-efuse",
217 .compatible = "rockchip,rockchip-efuse",
221 .compatible = "rockchip,rk3066a-efuse",
225 .compatible = "rockchip,rk3188-efuse",
229 .compatible = "rockchip,rk3228-efuse",
233 .compatible = "rockchip,rk3288-efuse",
237 .compatible = "rockchip,rk3368-efuse",
241 .compatible = "rockchip,rk3328-efuse",
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Drockchip-otp.c3 * Rockchip OTP Driver
5 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
256 .name = "rockchip-otp",
289 .compatible = "rockchip,px30-otp",
293 .compatible = "rockchip,rk3308-otp",
297 .compatible = "rockchip,rk3588-otp",
359 .name = "rockchip-otp",
365 MODULE_DESCRIPTION("Rockchip OTP driver");
/drivers/devfreq/
Drk3399_dmc.c3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
24 #include <soc/rockchip/pm_domains.h>
25 #include <soc/rockchip/rk3399_grf.h>
26 #include <soc/rockchip/rockchip_sip.h>
302 ret |= of_property_read_u32(np, "rockchip,pd-idle-ns", in rk3399_dmcfreq_of_props()
304 ret |= of_property_read_u32(np, "rockchip,sr-idle-ns", in rk3399_dmcfreq_of_props()
306 ret |= of_property_read_u32(np, "rockchip,sr-mc-gate-idle-ns", in rk3399_dmcfreq_of_props()
308 ret |= of_property_read_u32(np, "rockchip,srpd-lite-idle-ns", in rk3399_dmcfreq_of_props()
310 ret |= of_property_read_u32(np, "rockchip,standby-idle-ns", in rk3399_dmcfreq_of_props()
312 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", in rk3399_dmcfreq_of_props()
[all …]
/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-rk.c3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
109 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); in px30_set_to_rmii()
189 dev_err(dev, "Missing rockchip,grf property\n"); in rk3128_set_to_rgmii()
207 dev_err(dev, "Missing rockchip,grf property\n"); in rk3128_set_to_rmii()
220 dev_err(dev, "Missing rockchip,grf property\n"); in rk3128_set_rgmii_speed()
242 dev_err(dev, "Missing rockchip,grf property\n"); in rk3128_set_rmii_speed()
305 dev_err(dev, "Missing rockchip,grf property\n"); in rk3228_set_to_rgmii()
324 dev_err(dev, "Missing rockchip,grf property\n"); in rk3228_set_to_rmii()
341 dev_err(dev, "Missing rockchip,grf property\n"); in rk3228_set_rgmii_speed()
363 dev_err(dev, "Missing rockchip,grf property\n"); in rk3228_set_rmii_speed()
[all …]
/drivers/soc/rockchip/
Dio-domain.c3 * Rockchip IO Voltage Domain driver
21 * The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under
154 * According to Rockchip it's important to keep the SoC IO domain in rockchip_iodomain_notify()
512 .compatible = "rockchip,px30-io-voltage-domain",
516 .compatible = "rockchip,px30-pmu-io-voltage-domain",
520 .compatible = "rockchip,rk3188-io-voltage-domain",
524 .compatible = "rockchip,rk3228-io-voltage-domain",
528 .compatible = "rockchip,rk3288-io-voltage-domain",
532 .compatible = "rockchip,rk3328-io-voltage-domain",
536 .compatible = "rockchip,rk3368-io-voltage-domain",
[all …]
Dgrf.c3 * Rockchip Generic Register Files setup
138 .compatible = "rockchip,rk3036-grf",
141 .compatible = "rockchip,rk3128-grf",
144 .compatible = "rockchip,rk3228-grf",
147 .compatible = "rockchip,rk3288-grf",
150 .compatible = "rockchip,rk3328-grf",
153 .compatible = "rockchip,rk3368-grf",
156 .compatible = "rockchip,rk3399-grf",
159 .compatible = "rockchip,rk3566-pipe-grf",
162 .compatible = "rockchip,rk3588-sys-grf",
DKconfig5 # Rockchip Soc drivers
9 bool "Rockchip General Register Files support" if COMPILE_TEST
18 tristate "Rockchip IO domain support"
21 Say y here to enable support io domains on Rockchip SoCs. It is
26 bool "Rockchip generic power domain"
38 tristate "Rockchip DTPM hierarchy"
/drivers/cpufreq/
Dcpufreq-dt-platdev.c69 { .compatible = "rockchip,rk2928", },
70 { .compatible = "rockchip,rk3036", },
71 { .compatible = "rockchip,rk3066a", },
72 { .compatible = "rockchip,rk3066b", },
73 { .compatible = "rockchip,rk3188", },
74 { .compatible = "rockchip,rk3228", },
75 { .compatible = "rockchip,rk3288", },
76 { .compatible = "rockchip,rk3328", },
77 { .compatible = "rockchip,rk3366", },
78 { .compatible = "rockchip,rk3368", },
[all …]
/drivers/mfd/
Drk8xx-i2c.c3 * Rockchip RK808/RK818 Core (I2C) driver
5 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
161 { .compatible = "rockchip,rk805", .data = &rk805_data },
162 { .compatible = "rockchip,rk808", .data = &rk808_data },
163 { .compatible = "rockchip,rk809", .data = &rk809_data },
164 { .compatible = "rockchip,rk817", .data = &rk817_data },
165 { .compatible = "rockchip,rk818", .data = &rk818_data },
/drivers/staging/media/rkvdec/
DKconfig3 tristate "Rockchip Video Decoder driver"
14 Support for the Rockchip Video Decoder IP present on Rockchip SoCs,
17 will be called rockchip-vdec.
/drivers/media/platform/rockchip/rkisp1/
Drkisp1-csi.h3 * Rockchip ISP1 Driver - CSI-2 Receiver
8 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
9 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
/drivers/mmc/host/
Ddw_mmc-rockchip.c3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
80 * those can be made very accurately on all known Rockchip SoCs. in dw_mci_rk3288_set_ios()
120 * Rockchip SoCs), 90 degree offset will add a delay in dw_mci_rk3288_set_ios()
272 if (of_property_read_u32(np, "rockchip,desired-num-phases", in dw_mci_rk3288_parse_dt()
276 if (of_property_read_u32(np, "rockchip,default-sample-phase", in dw_mci_rk3288_parse_dt()
297 /* It is slot 8 on Rockchip SoCs */ in dw_mci_rockchip_init()
300 if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) { in dw_mci_rockchip_init()
335 { .compatible = "rockchip,rk2928-dw-mshc",
337 { .compatible = "rockchip,rk3288-dw-mshc",
405 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");

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