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/drivers/gpu/drm/ci/
Dgitlab-ci.yml86 - '/.gitlab-ci/farm-rules.yml'
126 .rules-anchors:
127 rules:
151 .scheduled_pipeline-rules:
152 rules:
158 .no_scheduled_pipelines-rules:
159 rules:
164 .build-rules:
165 rules:
166 - !reference [.no_scheduled_pipelines-rules, rules]
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Dcontainer.yml24 rules:
28 rules:
32 rules:
36 rules:
40 rules:
44 rules:
48 rules:
52 rules:
56 rules:
60 rules:
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Dtest.yml1 .test-rules:
2 rules:
7 - !reference [.no_scheduled_pipelines-rules, rules]
12 - .test-rules
70 - .test-rules
114 rules:
281 rules:
341 rules:
/drivers/net/dsa/qca/
Dqca8k-leds.c53 * 3 control rules for phy0-3 that applies to all their leds in qca8k_get_control_led_reg()
54 * 3 control rules for phy4 in qca8k_get_control_led_reg()
65 qca8k_parse_netdev(unsigned long rules, u32 *offload_trigger) in qca8k_parse_netdev() argument
68 if (test_bit(TRIGGER_NETDEV_TX, &rules)) in qca8k_parse_netdev()
70 if (test_bit(TRIGGER_NETDEV_RX, &rules)) in qca8k_parse_netdev()
72 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) in qca8k_parse_netdev()
74 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) in qca8k_parse_netdev()
76 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) in qca8k_parse_netdev()
78 if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) in qca8k_parse_netdev()
80 if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) in qca8k_parse_netdev()
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/drivers/net/ethernet/microchip/vcap/
DKconfig13 A VCAP is essentially a TCAM with rules consisting of
24 The VCAP implementation provides switchcore independent handling of rules
27 - Creating and deleting rules
28 - Updating and getting rules
32 access rules via the API in a platform independent way, with the
Dvcap_api.c931 list_for_each_entry(ri, &admin->rules, list) in vcap_rule_exists()
947 list_for_each_entry(ri, &admin->rules, list) in vcap_get_locked_rule()
965 list_for_each_entry(ri, &admin->rules, list) { in vcap_lookup_rule_by_cookie()
979 /* Get number of rules in a vcap instance lookup chain id range */
987 list_for_each_entry(elem, &admin->rules, list) { in vcap_admin_rule_count()
1658 /* Calculate the value used for chaining VCAP rules */
2111 * If the rule needs to be inserted between existing rules then move in vcap_insert_rule()
2112 * these rules to make room for the new rule and update their start in vcap_insert_rule()
2115 list_for_each_entry(iter, &admin->rules, list) { in vcap_insert_rule()
2131 list_add_tail(&duprule->list, &admin->rules); in vcap_insert_rule()
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Dvcap_api.h95 u16 default_cnt; /* number of default rules */
165 struct list_head rules; /* list of rules */ member
167 struct mutex lock; /* control access to rules */
/drivers/media/i2c/ccs/
Dccs-data.c435 struct ccs_rule *rules_base = NULL, *rules = NULL, *next_rule = NULL; in ccs_data_parse_rules() local
442 bin_alloc(bin, sizeof(*rules) * *__num_rules); in ccs_data_parse_rules()
495 rules = next_rule; in ccs_data_parse_rules()
513 rules->if_rules = if_rule; in ccs_data_parse_rules()
514 rules->num_if_rules = __num_if_rules; in ccs_data_parse_rules()
517 /* Check there was an if rule before any other rules */ in ccs_data_parse_rules()
518 if (bin->base && !rules) in ccs_data_parse_rules()
524 rules ? in ccs_data_parse_rules()
525 &rules->read_only_regs : NULL, in ccs_data_parse_rules()
526 rules ? in ccs_data_parse_rules()
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Dccs-data.h91 * @num_if_rules: Number of if rules
92 * @if_rules: If rules
189 * @num_sensor_rules: Number of rules for the sensor
190 * @sensor_rules: Rules for the sensor
196 * @num_module_rules: Number of rules for the module
197 * @module_rules: Rules for the module
/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dfs_ttc.c33 struct mlx5_ttc_rule rules[MLX5_NUM_TT]; member
47 if (!IS_ERR_OR_NULL(ttc->rules[i].rule)) { in mlx5_cleanup_ttc_rules()
48 mlx5_del_flow_rules(ttc->rules[i].rule); in mlx5_cleanup_ttc_rules()
49 ttc->rules[i].rule = NULL; in mlx5_cleanup_ttc_rules()
240 struct mlx5_ttc_rule *rules; in mlx5_generate_ttc_table_rules() local
246 rules = ttc->rules; in mlx5_generate_ttc_table_rules()
248 struct mlx5_ttc_rule *rule = &rules[tt]; in mlx5_generate_ttc_table_rules()
400 struct mlx5_ttc_rule *rules; in mlx5_generate_inner_ttc_table_rules() local
406 rules = ttc->rules; in mlx5_generate_inner_ttc_table_rules()
409 struct mlx5_ttc_rule *rule = &rules[tt]; in mlx5_generate_inner_ttc_table_rules()
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/drivers/net/phy/
Dmarvell.c2898 unsigned long rules; member
2904 .rules = BIT(TRIGGER_NETDEV_LINK),
2908 .rules = (BIT(TRIGGER_NETDEV_LINK) |
2914 .rules = (BIT(TRIGGER_NETDEV_RX) |
2919 .rules = (BIT(TRIGGER_NETDEV_RX) |
2924 .rules = BIT(TRIGGER_NETDEV_TX),
2928 .rules = BIT(TRIGGER_NETDEV_LINK),
2932 .rules = BIT(TRIGGER_NETDEV_LINK_1000),
2936 .rules = 0,
2943 .rules = (BIT(TRIGGER_NETDEV_LINK) |
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Dmediatek-ge-soc.c1223 unsigned long rules) in mt798x_phy_led_hw_is_supported() argument
1229 if (rules & ~supported_triggers) in mt798x_phy_led_hw_is_supported()
1236 unsigned long *rules) in mt798x_phy_led_hw_control_get() argument
1276 if (!rules) in mt798x_phy_led_hw_control_get()
1280 *rules |= BIT(TRIGGER_NETDEV_LINK); in mt798x_phy_led_hw_control_get()
1283 *rules |= BIT(TRIGGER_NETDEV_LINK_10); in mt798x_phy_led_hw_control_get()
1286 *rules |= BIT(TRIGGER_NETDEV_LINK_100); in mt798x_phy_led_hw_control_get()
1289 *rules |= BIT(TRIGGER_NETDEV_LINK_1000); in mt798x_phy_led_hw_control_get()
1292 *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); in mt798x_phy_led_hw_control_get()
1295 *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); in mt798x_phy_led_hw_control_get()
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/drivers/net/ethernet/netronome/nfp/flower/
Dconntrack.c709 static int nfp_fl_merge_actions_offload(struct flow_rule **rules, in nfp_fl_merge_actions_offload() argument
722 num_actions += rules[i]->action.num_entries; in nfp_fl_merge_actions_offload()
732 if (rules[num_rules - 1]->action.num_entries != 0) in nfp_fl_merge_actions_offload()
733 tmp_stats = rules[num_rules - 1]->action.entries[0].hw_stats; in nfp_fl_merge_actions_offload()
736 a_rule->match = rules[0]->match; in nfp_fl_merge_actions_offload()
743 if (flow_rule_match_key(rules[j], FLOW_DISSECTOR_KEY_BASIC)) { in nfp_fl_merge_actions_offload()
753 flow_rule_match_basic(rules[j], &match); in nfp_fl_merge_actions_offload()
755 a_rule->match = rules[j]->match; in nfp_fl_merge_actions_offload()
760 for (i = 0; i < rules[j]->action.num_entries; i++) { in nfp_fl_merge_actions_offload()
761 a_in = &rules[j]->action.entries[i]; in nfp_fl_merge_actions_offload()
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Dmain.h267 * @flow_table: Hash table used to store flower rules
268 * @stats: Stored stats updates for flower rules
284 * @active_mem_unit: Current active memory unit for flower rules
285 * @total_mem_units: Total number of available memory units for flower rules
286 * @internal_ports: Internal port ids used in offloaded rules
292 * @pre_tun_rule_cnt: Number of pre-tunnel rules offloaded
424 * @ref_count: number of rules currently using this IP
/drivers/net/ethernet/mellanox/mlx5/core/
DKconfig53 flow rules to direct traffic into arbitrary rx queue via ethtool set/get_rxnfc
84 offloading rules for traffic between such ports. Supports VLANs (trunk and
107 Say Y here if you want to support offloading connection tracking rules
118 Say Y here if you want to support offloading sample rules via tc
120 If set to N, will not be able to configure tc rules with sample
/drivers/gpu/drm/etnaviv/
Dstate_blt.xml.h6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
10 The rules-ng-ng source files this header was generated from are:
Dcmdstream.xml.h6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
10 The rules-ng-ng source files this header was generated from are:
/drivers/net/ethernet/mellanox/mlx5/core/lag/
Dport_sel.c16 u8 rules) in mlx5_create_hash_flow_group() argument
29 MLX5_SET(create_flow_group_in, in, end_flow_index, rules - 1); in mlx5_create_hash_flow_group()
86 lag_definer->rules[idx] = mlx5_add_flow_rules(lag_definer->ft, in mlx5_lag_create_port_sel_table()
89 if (IS_ERR(lag_definer->rules[idx])) { in mlx5_lag_create_port_sel_table()
90 err = PTR_ERR(lag_definer->rules[idx]); in mlx5_lag_create_port_sel_table()
94 mlx5_del_flow_rules(lag_definer->rules[idx]); in mlx5_lag_create_port_sel_table()
352 mlx5_del_flow_rules(lag_definer->rules[idx]); in mlx5_lag_destroy_definer()
586 err = mlx5_modify_rule_destination(def->rules[idx], &dest, NULL); in __mlx5_lag_modify_definers_destinations()
Dport_sel.h13 /* Each port has ldev->buckets number of rules and they are arrange in
16 struct mlx5_flow_handle *rules[MLX5_MAX_PORTS * MLX5_LAG_MAX_HASH_BUCKETS]; member
/drivers/net/ethernet/sfc/
Dtc.h267 * @match_action_ht: Hashtable of TC match-action rules
268 * @lhs_rule_ht: Hashtable of TC left-hand (act ct & goto chain) rules
285 * @dflt: Match-action rules for default switching; at priority
289 * @facts: Fallback action-set-lists for unready rules. Named by *egress* port
290 * @facts.pf: action-set-list for unready rules on PF netdev, hence applying to
292 * @facts.reps: action-set-list for unready rules on representors, hence
/drivers/net/wireless/ath/ath12k/
Dreg.c376 /* Use the flags of both the rules */ in ath12k_reg_intersect_rules()
379 /* To be safe, lts use the max cac timeout of both rules */ in ath12k_reg_intersect_rules()
397 /* Find the number of intersecting rules to allocate new regd memory */ in ath12k_regd_intersect()
577 /* FIXME: Currently taking reg rules for 6G only from Indoor AP mode list. in ath12k_reg_build_regd()
587 /* Add max additional rules to accommodate weather radar band */ in ath12k_reg_build_regd()
607 * send these rules in order(2G rules first and then 5G) in ath12k_reg_build_regd()
624 * for all 5G rules here. The regulatory core performs in ath12k_reg_build_regd()
651 * need to update that for other rules. in ath12k_reg_build_regd()
/drivers/net/ethernet/intel/ice/
Dice_arfs.c96 * ice_arfs_del_flow_rules - delete the rules passed in from HW
97 * @vsi: VSI for the flow rules that need to be deleted
100 * Loop through the delete list passed in and remove the rules from HW. After
132 * ice_arfs_add_flow_rules - add the rules passed in from HW
133 * @vsi: VSI for the flow rules that need to be added
136 * Loop through the add list passed in and remove the rules from HW. After each
200 * ice_arfs_update_flow_rules - add/delete aRFS rules in HW
211 * is expected to add/delete rules on the add_list/del_list respectively.
355 * to check if perfect (4-tuple) flow rules are currently in place by Flow
/drivers/net/wireless/ath/ath11k/
Dreg.c415 /* Use the flags of both the rules */ in ath11k_reg_intersect_rules()
418 /* To be safe, lts use the max cac timeout of both rules */ in ath11k_reg_intersect_rules()
436 /* Find the number of intersecting rules to allocate new regd memory */ in ath11k_regd_intersect()
625 /* FIXME: Currently taking reg rules for 6 GHz only from Indoor AP mode list. in ath11k_reg_build_regd()
634 /* Add max additional rules to accommodate weather radar band */ in ath11k_reg_build_regd()
654 * send these rules in order(2 GHz rules first and then 5 GHz) in ath11k_reg_build_regd()
671 * for all 5G rules here. The regulatory core performs in ath11k_reg_build_regd()
699 * need to update that for other rules. in ath11k_reg_build_regd()
/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
Degress_ofld.c83 "vport[%d] configure prio tag egress rules\n", vport->vport); in esw_acl_egress_ofld_rules_create()
217 esw_debug(esw->dev, "vport[%d] configure egress rules\n", vport->vport); in esw_acl_egress_ofld_setup()
251 /* Cleanup and recreate rules WITHOUT fwd2vport of active vport */ in mlx5_esw_acl_egress_vport_bond()
255 /* Cleanup and recreate all rules + fwd2vport rule of passive vport to forward */ in mlx5_esw_acl_egress_vport_bond()
/drivers/net/dsa/sja1105/
Dsja1105_flower.c12 list_for_each_entry(rule, &priv->flow_block.rules, list) in sja1105_rule_find()
94 list_add(&rule->list, &priv->flow_block.rules); in sja1105_setup_bcast_policer()
166 list_add(&rule->list, &priv->flow_block.rules); in sja1105_setup_tc_policer()
525 INIT_LIST_HEAD(&priv->flow_block.rules); in sja1105_flower_setup()
537 list_for_each_safe(pos, n, &priv->flow_block.rules) { in sja1105_flower_teardown()

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