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/Documentation/devicetree/bindings/reset/
Dreset.txt1 = Reset Signal Device Tree Bindings =
8 Hardware blocks typically receive a reset signal. This signal is generated by
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
20 A word on where to place reset signal consumers in device tree: It is possible
21 in hardware for a reset signal to affect multiple logically separate HW blocks
22 at once. In this case, it would be unwise to represent this reset signal in
26 children of the bus are affected by the reset signal, or an individual HW
29 rather than to slavishly enumerate the reset signal that affects each HW
49 for each reset signal that affects the device, or that the
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/Documentation/ABI/testing/
Dsysfs-timecard24 IRIG adjustments from external IRIG-B signal
25 DCF adjustments from external DCF signal
32 input signal.
35 10Mhz signal is used as the 10Mhz reference clock
36 PPS1 signal is sent to the PPS1 selector
37 PPS2 signal is sent to the PPS2 selector
38 TS1 signal is sent to timestamper 1
39 TS2 signal is sent to timestamper 2
40 TS3 signal is sent to timestamper 3
41 TS4 signal is sent to timestamper 4
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Dsysfs-bus-counter94 The output signal is initially low, and will remain low
95 until the counter reaches zero. The output signal then
100 The output signal is initially high. The output signal
101 will go low by a trigger input signal, and will remain
105 value and setting the output signal low, thus starting
109 The output signal is initially high. When the counter
110 has decremented to 1, the output signal goes low for one
111 clock pulse. The output signal then goes high again, the
116 The output signal is initially high.
120 expires, the output signal changes value and the
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Dsysfs-class-led-trigger-netdev26 Signal the link state of the named network device.
40 Signal transmission of data on the named network device.
45 in interval to signal transmission.
55 Signal reception of data on the named network device.
60 in interval to signal reception.
83 Signal the link speed state of 10Mbps of the named network device.
96 Signal the link speed state of 100Mbps of the named network device.
109 Signal the link speed state of 1000Mbps of the named network device.
122 Signal the link half duplex state of the named network device.
135 Signal the link full duplex state of the named network device.
Dsysfs-bus-iio-timer-stm3212 The Counter Enable signal CNT_EN is used
22 OC1REF signal is used as trigger output.
24 OC2REF signal is used as trigger output.
26 OC3REF signal is used as trigger output.
28 OC4REF signal is used as trigger output.
33 OC5REF signal is used as trigger output.
35 OC6REF signal is used as trigger output.
122 Counting is enabled when connected trigger signal
Dsysfs-class-pwm55 Sets the PWM signal period in nanoseconds.
62 Sets the PWM signal duty cycle in nanoseconds.
69 Sets the output polarity of the PWM signal to "normal" or
77 Enable/disable the PWM signal.
86 Capture information about a PWM signal. The output format is a
/Documentation/devicetree/bindings/leds/
Dleds-bcm6328.yaml25 should be controlled by a hardware signal instead of the MODE register value,
29 explained later in brcm,link-signal-sources). Even if a LED is hardware
53 description: Makes clock signal active low.
57 description: Makes data signal active low.
89 brcm,link-signal-sources:
94 An array of hardware link signal sources. Up to four link hardware
97 7 may be muxed to LEDs 4 to 7. A signal can be muxed to more than one
98 LED, and one LED can have more than one source signal.
100 brcm,activity-signal-sources:
105 An array of hardware activity signal sources. Up to four activity
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/Documentation/driver-api/
Dgeneric-counter.rst29 * Signal:
33 Association of a Signal, and evaluation trigger, with a Count.
38 SIGNAL section in Theory
40 A Signal represents a stream of data. This is the input data that is
42 signal output line of a rotary encoder. Not all counter devices provide
43 user access to the Signal data, so exposure is optional for drivers.
45 When the Signal data is available for user access, the Generic Counter
46 interface provides the following available signal values:
49 Signal line is in a low state.
52 Signal line is in a high state.
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/Documentation/devicetree/bindings/watchdog/
Daspeed-wdt.txt38 - aspeed,external-signal: If property is present then signal is sent to
40 specified no external signal is sent.
41 - aspeed,ext-pulse-duration: External signal pulse duration in microseconds
44 - aspeed,ext-push-pull: If aspeed,external-signal is present, set the pin's
46 - aspeed,ext-active-high: If aspeed,external-signal is present and and the pin
56 aspeed,external-signal;
/Documentation/userspace-api/media/v4l/
Dext-ctrls-rf-tuner.rst14 converts that received signal to lower intermediate frequency (IF) or
43 Filter(s) on tuner signal path are used to filter signal according
59 The RF amplifier is the very first amplifier on the receiver signal
68 signal path. It is located very close to tuner antenna input. Used
75 Mixer gain is second gain stage on the RF tuner signal path. It is
76 located inside mixer block, where RF signal is down-converted by the
81 IF gain is last gain stage on the RF tuner signal path. It is
82 located on output of RF tuner. It controls signal level of
Dvidioc-query-dv-timings.rst57 If the timings could not be detected because there was no signal, then
58 ENOLINK is returned. If a signal was detected, but it was unstable and
59 the receiver could not lock to the signal, then ``ENOLCK`` is returned. If
60 the receiver could lock to the signal, but the format is unsupported
79 No timings could be detected because no signal was found.
82 The signal was unstable and the hardware could not lock on to it.
/Documentation/devicetree/bindings/display/panel/
Dpanel-common.yaml84 (hot plug detect) signal, but the signal isn't hooked up so we should
103 Specifier for a GPIO connected to the panel enable control signal. The
104 enable signal is active high and enables operation of the panel. This
106 signal, which is a negated version of the enable signal. Active low enable
110 Note that the enable signal control panel operation only and must not be
111 confused with a backlight enable signal.
116 Specifier for a GPIO connected to the panel reset control signal.
117 The reset signal is active low and resets the panel internal logic
124 GPIO spec for the tearing effect synchronization signal.
125 The tearing effect signal is active high. Active low signals can be
/Documentation/driver-api/gpio/
Dintro.rst30 digital signal. They are provided from many kinds of chips, and are familiar
83 It is natural to assume that a GPIO is "active" when its output signal is 1
84 ("high"), and inactive when it is 0 ("low"). However in practice the signal of a
89 means "active") so that drivers only need to worry about the logical signal and
94 Sometimes shared signals need to use "open drain" (where only the low signal
95 level is actually driven), or "open source" (where only the high signal level is
97 used for TTL. A pullup or pulldown resistor causes the high or low signal level.
101 One common example of an open drain signal is a shared active-low IRQ line.
109 **LOW**: ``gpiod_direction_output(gpio, 0)`` ... this drives the signal and
113 the pullup (or some other device) controls the signal.
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/Documentation/devicetree/bindings/sound/
Dcs35l35.txt26 - cirrus,audio-channel : Set Location of Audio Signal on Serial Port
30 - cirrus,advisory-channel : Set Location of Advisory Signal on Serial Port
34 - cirrus,shared-boost : Boolean to enable ClassH tracking of Advisory Signal
105 Optional Monitor Signal Format sub-node:
107 The cs35l35 node can have a single "cirrus,monitor-signal-format" sub-node
113 -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formatting
120 for each monitoring signal.
123 scale of the IMON monitor signal.
126 of the VMON monitor signal.
129 of the VPMON monitor signal.
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/Documentation/devicetree/bindings/serial/
Dsnps-dw-apb-uart.yaml91 description: Override the DCD modem status signal. This signal will
98 description: Override the DTS modem status signal. This signal will
105 description: Override the CTS modem status signal. This signal will
112 description: Override the RI modem status signal. This signal will always
Drs485.yaml9 description: The RTS signal is capable of automatically controlling line
22 - description: Delay between rts signal and beginning of data sent in
26 - description: Delay between end of data sent and rts signal in milliseconds.
41 description: Polarity of receiver enable signal (when separate from RTS).
60 signal can be used to control the RX part of an RS485 transceiver. Thereby
/Documentation/devicetree/bindings/net/
Dsff,sfp.yaml36 presence input gpio signal, active (module absent) high. Must not be
42 GPIO phandle and a specifier of the Receiver Loss of Signal Indication
43 input gpio signal, active (signal lost) high
49 signal, active (fault condition) high
55 signal, active (Tx disable) high
61 output gpio signal, low - low Rx rate, high - high Rx rate Must not be
68 output gpio signal (SFP+ only), low - low Tx rate, high - high Tx rate. Must
Dhisilicon-hix5hd2-gmac.txt23 - resets: should contain the phandle to the MAC core reset signal(optional),
24 the MAC interface reset signal(optional)
25 and the PHY reset signal(optional).
26 - reset-names: contain the reset signal name "mac_core"(optional),
28 - hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
Dhisilicon-femac.txt13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
19 - hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
/Documentation/devicetree/bindings/mailbox/
Dqcom-ipcc.yaml15 addressing scheme called protocol, client and signal. For example, consider an
18 a case, the client would be Modem (client-id is 2) and the signal would be
19 SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
50 The first cell is the client-id, the second cell is the signal-id and the
56 The first cell is the client-id, and the second cell is the signal-id.
/Documentation/arch/x86/
Dxstate.rst18 alternate signal stacks, often using MINSIGSTKSZ which is typically 2KB.
19 That stack must be able to store at *least* the signal frame that the
20 kernel sets up before jumping into the signal handler. That signal frame
23 However, that means that the size of signal stacks is dynamic, not static,
65 are large enough to accommodate the resulting large signal frame. It
138 Dynamic features in signal frames
141 Dynamcally enabled features are not written to the signal frame upon signal
144 configuration. Signal handlers can examine the XSAVE buffer's XSTATE_BV
/Documentation/devicetree/bindings/memory-controllers/
Dst,stm32-fmc2-ebi-props.yaml53 description: Wait signal polarity (NWAIT signal active high).
58 description: The NWAIT signal indicates wheither the data from the
60 the device in synchronous mode. By default, the NWAIT signal is
65 description: The NWAIT signal is enabled (its level is taken into
67 if asserted). By default, the NWAIT signal is disabled.
71 description: The NWAIT signal is taken into account during asynchronous
72 transactions. By default, the NWAIT signal is not taken into account
110 description: This property defines the FMC_CLK output signal period in
/Documentation/devicetree/bindings/serio/
Dps2-gpio.yaml18 the gpio used for the data signal - this should be flagged as
20 from <dt-bindings/gpio/gpio.h> since the signal is open drain by
26 the gpio used for the clock signal - this should be flagged as
28 from <dt-bindings/gpio/gpio.h> since the signal is open drain by
/Documentation/userspace-api/media/dvb/
Dfe-read-snr.rst31 The signal-to-noise ratio is stored into \*snr.
36 This ioctl call returns the signal-to-noise ratio for the signal
/Documentation/arch/arm64/
Dsme.rst115 5. Signal handling
118 * Signal handlers are invoked with streaming mode and ZA disabled.
120 * A new signal frame record TPIDR2_MAGIC is added formatted as a struct
121 tpidr2_context to allow access to TPIDR2_EL0 from signal handlers.
123 * A new signal frame record za_context encodes the ZA register contents on
124 signal delivery. [1]
126 * The signal frame record for ZA always contains basic metadata, in particular
146 * If ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will
149 * The signal record for ZTn has magic ZT_MAGIC (0x5a544e01) and consists of a
150 standard signal frame header followed by a struct zt_context specifying
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