Searched full:signals (Results 1 – 25 of 301) sorted by relevance
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| /Documentation/devicetree/bindings/reset/ |
| D | reset.txt | 3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
24 may be reset. Instead, reset signals should be represented in the DT node
27 block node for dedicated reset signals. The intent of this binding is to give
28 appropriate software access to the reset signals in order to manage the HW,
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| /Documentation/trace/coresight/ |
| D | coresight-ect.rst | 14 individual input and output hardware signals known as triggers to and from
50 The hardware trigger signals can also be connected to non-CoreSight devices
72 capable of generating or using trigger signals.::
100 Individual trigger connection information. This describes trigger signals for
108 * ``in_types`` : functional types for in signals.
109 * ``out_signals`` : output trigger signals for this connection.
110 * ``out_types`` : functional types for out signals.
127 If a connection has zero signals in either the 'in' or 'out' triggers then
177 * ``chan_free``: Show channels with no attached signals.
185 dangerous output signals to be set.
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| /Documentation/devicetree/bindings/display/panel/ |
| D | panel-common.yaml | 96 # and timing of those control signals are device-specific and left for panel
98 # used for panels that implement compatible control signals.
107 signals (or active high power down signals) can be supported by inverting
118 while active. Active high reset signals can be supported by inverting the
125 The tearing effect signal is active high. Active low signals can be
143 # backlight control through GPIO, PWM or other signals connected to an external
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| /Documentation/gpu/amdgpu/display/ |
| D | dcn-overview.rst | 67 2. Global sync signals (green): It is a set of synchronization signals composed
70 4. Sideband signals: All other signals that do not fit the previous one.
72 These signals are essential and play an important role in DCN. Nevertheless,
197 These atomic register updates are driven by global sync signals in DCN. In
199 signals page flip and vblank events it is helpful to understand how global sync
202 Global sync consists of three signals, VSTARTUP, VUPDATE, and VREADY. These are
206 The global sync signals always happen during VBlank, are independent from the
210 or userspace clients as it signals the point at which hardware latches to
218 The below picture illustrates the global sync signals:
222 These signals affect core DCN behavior. Programming them incorrectly will lead
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| /Documentation/devicetree/bindings/gpio/ |
| D | sprd,gpio-eic.yaml | 24 connections. A debounce mechanism is used to capture the input signals'
32 The EIC-latch sub-module is used to latch some special power down signals
34 clock to capture signals.
36 The EIC-async sub-module uses a 32kHz clock to capture the short signals
41 when detecting input signals.
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| D | nvidia,tegra186-gpio.yaml | 21 and read/write the value of, numerous GPIO signals. Routing of GPIO signals
35 b) GPIO registers, which allow manipulation of the GPIO signals. In some
60 Each GPIO controller can generate a number of interrupt signals. Each
62 ports. Thus, the number of interrupt signals generated by a controller
67 Each GPIO controller in fact generates multiple interrupts signals for
69 one of the interrupt signals generated by a set-of-ports. The intent is
72 The status of each of these per-port-set signals is reported via a
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| /Documentation/driver-api/ |
| D | hsi.rst | 15 The serial protocol uses two signals, DATA and FLAG as combined data and clock
16 signals and an additional READY signal for flow control. An additional WAKE
17 signal can be used to wakeup the chips from standby modes. The signals are
18 commonly prefixed by AC for signals going from the application die to the
19 cellular die and CA for signals going the other way around.
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| D | ptp.rst | 25 - Period output signals configurable from user space
99 - 3 Periodic signals (optional interrupt)
107 - GPIO outputs can produce periodic signals
119 - Programmable output periodic signals
131 periodic signals.
134 periodic signals.
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| D | generic-counter.rst | 80 A counter is defined as a set of input signals associated with count
82 input signals as defined by the respective count functions. Within the
84 each associated with a set of Signals, whose respective Synapse
93 Synapses; i.e. the count data for a set of Signals. The Generic
111 A pair of quadrature encoding signals are evaluated to determine
135 Any state transition on either quadrature pair signals updates the
167 many Signals may be associated with even a single Count. For example, a
183 In this example, two Signals (quadrature encoder lines A and B) are
188 encoder counter device; the Count, Signals, and Synapses simply
191 Signals associated with the same Count can have differing Synapse action
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| D | miscellaneous.rst | 31 PWM signals. A controller that provides one or more PWM signals is
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-cti.yaml | 19 output hardware trigger signals. CTIs can have a maximum number of input and
20 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
30 In general the connections between CTI and components via the trigger signals
40 binding can be declared with no explicit trigger signals. This will result
57 signals to GEN_IO.
59 Note that some hardware trigger signals can be connected to non-CoreSight
134 A trigger connections child node which describes the trigger signals
157 signals. Types in this array match to the corresponding signal in the
174 signals. Types in this array match to the corresponding signal
183 List of CTI trigger out signals that will be blocked from becoming
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| /Documentation/devicetree/bindings/usb/ |
| D | brcm,usb-pinmap.yaml | 22 description: Interrupt for signals mirrored to out-gpios.
27 description: Array of one or two GPIO pins used for input signals.
39 description: Array of one GPIO pin used for output signals.
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| /Documentation/devicetree/bindings/media/ |
| D | st-rc.txt | 11 protocol used for receiving remote control signals. rx-mode should
14 protocol used for transmitting remote control signals. tx-mode should
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| /Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-common.yaml | 28 CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such
47 Endpoint controllers IRQ-signals, the later interface is obviously
49 messages signalling. The System Information IRQ signals are mainly
95 signals (except resets) are synchronous to this clock.
133 signals required to be de-asserted to properly activate the controller
134 sub-parts. All of these signals can be divided into two sub-groups':'
136 are supposed to reset. Note the platforms may have some of these signals
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-cti | 35 Description: (Read) Input trigger signals from connected device <N>
41 Description: (Read) Functional types for the input trigger signals
48 Description: (Read) Output trigger signals to connected device <N>
54 Description: (Read) Functional types for the output trigger signals
129 Description: (Read) read current status of input trigger signals
135 Description: (Read) read current status of output trigger signals.
214 Description: (Read) show channels with no attached trigger signals.
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| /Documentation/devicetree/bindings/misc/ |
| D | ti,j721e-esm.yaml | 16 controller would do. The safety signals have their separate paths within
19 simplest configuration the signals are just routed to reset the SoC.
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-bcm6328.yaml | 27 is usually 1:1 for hardware to LED signals, but through the activity/link
95 signals can get muxed into these LEDs. Only valid for LEDs 0 to 7,
96 where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and signals 4 to
106 hardware signals can get muxed into these LEDs. Only valid for LEDs 0
107 to 7, where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and
108 signals 4 to 7 may be muxed to LEDs 4 to 7. A signal can be muxed to
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | tvp5150.txt | 4 (and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV
55 - sdtv-standards: Set the possible signals to which the hardware tries to lock
67 sdtv-standards = <SDTV_STD_PAL_M>; /* limit to pal-m signals */
79 sdtv-standards = <SDTV_STD_NTSC_M>; /* limit to ntsc-m signals */
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| /Documentation/driver-api/gpio/ |
| D | intro.rst | 58 - Inputs can often be used as IRQ signals, often edge triggered but
94 Sometimes shared signals need to use "open drain" (where only the low signal
102 Also, bidirectional data bus signals sometimes use open drain signals.
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| /Documentation/devicetree/bindings/input/ |
| D | goodix,gt7375p.yaml | 46 The supply on the main board needed to power up IO signals going
48 itself as long as it allows the main board to make signals compatible
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| /Documentation/devicetree/bindings/sound/ |
| D | wlf,arizona.yaml | 31 signals. Valid values are 0 (Differential), 1 (Single-ended) and
34 to the number of input signals. If values less than the number of
35 input signals, elements that have not been specified are set to 0 by
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| D | nvidia,tegra210-dmic.yaml | 11 Density Modulation (PDM) input devices. It converts PDM signals to
12 Pulse Coded Modulation (PCM) signals. DMIC can be viewed as a PDM
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | microchip,sparx5-sgpio.yaml | 16 connect control signals from SFP modules and to act as an LED
44 match the hardware configuration in order for signals to be
66 getting control signals back and forth between external shift
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| /Documentation/devicetree/bindings/mux/ |
| D | adi,adg792a.txt | 22 States 0 through 3 correspond to signals A through D in the datasheet.
54 * the adc is differential, thus needing two signals to be muxed
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| /Documentation/userspace-api/media/v4l/ |
| D | yuv-formats.rst | 9 YUV is the format native to TV broadcast and composite video signals. It
12 *color difference* signals, this way the green component can be
17 was added to transmit the color difference signals.
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