| /Documentation/devicetree/bindings/mips/ |
| D | ralink.yaml | 7 title: Ralink SoC based Platforms
13 Boards with a Ralink SoC shall have the following properties.
20 - description: Boards with Ralink RT2880 SoC
24 - const: ralink,rt2880-soc
26 - description: Boards with Ralink RT3050 SoC
28 - const: ralink,rt3050-soc
30 - description: Boards with Ralink RT3052 SoC
34 - const: ralink,rt3052-soc
36 - description: Boards with Ralink RT3350 SoC
38 - const: ralink,rt3350-soc
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| /Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-soc-glue.yaml | 4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
7 title: Socionext UniPhier SoC-glue logic
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
22 - socionext,uniphier-pro5-soc-glue
23 - socionext,uniphier-pxs2-soc-glue
24 - socionext,uniphier-sld8-soc-glue
25 - socionext,uniphier-ld11-soc-glue
26 - socionext,uniphier-ld20-soc-glue
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| D | socionext,uniphier-soc-glue-debug.yaml | 4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
7 title: Socionext UniPhier SoC-glue logic debug part
13 SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
21 - socionext,uniphier-ld4-soc-glue-debug
22 - socionext,uniphier-pro4-soc-glue-debug
23 - socionext,uniphier-pro5-soc-glue-debug
24 - socionext,uniphier-pxs2-soc-glue-debug
25 - socionext,uniphier-sld8-soc-glue-debug
26 - socionext,uniphier-ld11-soc-glue-debug
27 - socionext,uniphier-ld20-soc-glue-debug
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | imx8m-soc.yaml | 4 $id: http://devicetree.org/schemas/soc/imx/imx8m-soc.yaml#
7 title: NXP i.MX8M Series SoC
13 NXP i.MX8M series SoCs contain fuse entries from which SoC Unique ID can be
29 "^soc@[0-9a-f]+$":
35 - fsl,imx8mm-soc
36 - fsl,imx8mn-soc
37 - fsl,imx8mp-soc
38 - fsl,imx8mq-soc
53 description: Phandle to the SOC Unique ID provided by a nvmem node
76 soc@0 {
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| /Documentation/process/ |
| D | maintainer-soc.rst | 4 SoC Subsystem
10 The SoC subsystem is a place of aggregation for SoC-specific code.
16 * SoC-specific drivers across architectures, in particular for 32- & 64-bit
19 These "SoC-specific drivers" do not include clock, GPIO etc drivers that have
20 other top-level maintainers. The drivers/soc/ directory is generally meant
21 for kernel-internal drivers that are used by other drivers to provide SoC-
22 specific functionality like identifying an SoC revision or interfacing with
25 The SoC subsystem also serves as an intermediate location for changes to
27 of new platforms, or the removal of existing ones, often go through the SoC
30 The main SoC tree is housed on git.kernel.org:
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| /Documentation/devicetree/bindings/arm/ti/ |
| D | k3.yaml | 7 title: Texas Instruments K3 Multicore SoC architecture
13 Platforms based on Texas Instruments K3 Multicore SoC architecture
22 - description: K3 AM62A7 SoC
28 - description: K3 AM62P5 SoC and Boards
34 - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
40 - description: K3 AM625 SoC
48 - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards
58 - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT
68 - description: K3 AM642 SoC
75 - description: K3 AM642 SoC PHYTEC phyBOARD-Electra
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-soc | 6 System-on-Chip (SoC) device on a running platform. Information
7 regarding each SoC can be obtained by reading sysfs files. This
10 The directory created for each SoC will also house information
12 It has been agreed that if an SoC device exists, its supported
13 devices would be better suited to appear as children of that SoC.
19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
57 Read-only attribute supported by most SoCs. Contains the SoC's
65 ST-Ericsson's chips this contains the SoC serial number.
68 this will contain the SOC ID appended to the family attribute
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| /Documentation/devicetree/bindings/soc/litex/ |
| D | litex,soc-controller.yaml | 5 $id: http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#
8 title: LiteX SoC Controller driver
11 This is the SoC Controller driver for the LiteX SoC Builder.
22 const: litex,soc-controller
35 soc_ctrl0: soc-controller@f0000000 {
36 compatible = "litex,soc-controller";
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| /Documentation/devicetree/bindings/arm/ |
| D | amlogic.yaml | 7 title: Amlogic SoC based Platforms
28 - description: Boards with the Amlogic Meson6 SoC
34 - description: Boards with the Amlogic Meson8 SoC
40 - description: Boards with the Amlogic Meson8m2 SoC
46 - description: Boards with the Amlogic Meson8b SoC
54 - description: Boards with the Amlogic Meson GXBaby SoC
76 - description: Boards with the Amlogic Meson GXL S805X SoC
84 - description: Boards with the Amlogic Meson GXL S905W SoC
93 - description: Boards with the Amlogic Meson GXL S905X SoC
105 - description: Boards with the Amlogic Meson GXL S905D SoC
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| D | realtek.yaml | 17 # RTD1195 SoC based boards
24 # RTD1293 SoC based boards
30 # RTD1295 SoC based boards
39 # RTD1296 SoC based boards
45 # RTD1395 SoC based boards
52 # RTD1619 SoC based boards
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| D | apple.yaml | 15 This currently includes devices based on the "M1" SoC:
22 Devices based on the "M2" SoC:
47 <socid> is the lowercased SoC ID. Apple uses at least *five* different
53 - SoC ID ("T8103")
56 Devicetrees should use the lowercased SoC ID, to avoid confusion if
68 - description: Apple M1 SoC based platforms
79 - description: Apple M2 SoC based platforms
88 - description: Apple M1 Pro SoC based platforms
96 - description: Apple M1 Max SoC based platforms
105 - description: Apple M1 Ultra SoC based platforms
|
| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
54 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
55 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
56 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
57 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
58 "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
59 "marvell,dove-core-clock" - for Dove SoC core clocks
60 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
61 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
62 "marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
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| /Documentation/arch/arm/spear/ |
| D | overview.rst | 19 - SPEAr3XX (3XX SOC series, based on ARM9)
20 - SPEAr300 (SOC)
22 - SPEAr310 (SOC)
24 - SPEAr320 (SOC)
26 - SPEAr6XX (6XX SOC series, based on ARM9)
27 - SPEAr600 (SOC)
29 - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
30 - SPEAr1310 (SOC)
32 - SPEAr1340 (SOC)
57 mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine specific
|
| /Documentation/sound/kernel-api/ |
| D | alsa-driver-api.rst | 99 .. kernel-doc:: include/sound/soc.h
100 .. kernel-doc:: sound/soc/soc-core.c
101 .. kernel-doc:: sound/soc/soc-devres.c
102 .. kernel-doc:: sound/soc/soc-component.c
103 .. kernel-doc:: sound/soc/soc-pcm.c
104 .. kernel-doc:: sound/soc/soc-ops.c
105 .. kernel-doc:: sound/soc/soc-compress.c
109 .. kernel-doc:: sound/soc/soc-dapm.c
113 .. kernel-doc:: sound/soc/soc-generic-dmaengine-pcm.c
126 .. kernel-doc:: sound/soc/soc-jack.c
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| /Documentation/devicetree/bindings/arm/socionext/ |
| D | uniphier.yaml | 17 - description: LD4 SoC boards
22 - description: Pro4 SoC boards
29 - description: Pro5 SoC boards
35 - description: sLD8 SoC boards
40 - description: PXs2 SoC boards
46 - description: LD6b SoC boards
51 - description: LD11 SoC boards
57 - description: LD20 SoC boards
64 - description: PXs3 SoC boards
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,mvebu-pinctrl.txt | 1 * Marvell SoC pinctrl core driver for mpp
4 (mpp) to a specific function. For each SoC family there is a SoC specific
11 A Marvell SoC pin configuration node is a node of a group of pins which can
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
23 common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
24 valid pin/pin group names and available function names for each SoC.
|
| /Documentation/devicetree/bindings/net/ |
| D | renesas,ether.yaml | 20 - renesas,gether-r8a7740 # device is a part of R8A7740 SoC
21 - renesas,gether-r8a77980 # device is a part of R8A77980 SoC
22 - renesas,ether-r7s72100 # device is a part of R7S72100 SoC
23 - renesas,ether-r7s9210 # device is a part of R7S9210 SoC
26 - renesas,ether-r8a7778 # device is a part of R8A7778 SoC
27 - renesas,ether-r8a7779 # device is a part of R8A7779 SoC
32 - renesas,ether-r8a7742 # device is a part of R8A7742 SoC
33 - renesas,ether-r8a7743 # device is a part of R8A7743 SoC
34 - renesas,ether-r8a7745 # device is a part of R8A7745 SoC
35 - renesas,ether-r8a7790 # device is a part of R8A7790 SoC
[all …]
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| /Documentation/devicetree/bindings/ptp/ |
| D | brcm,ptp-dte.txt | 5 and the SoC compatibility string. The SoC
6 compatibility string is to handle SoC specific
10 SoC compatibility strings:
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
|
| /Documentation/devicetree/bindings/arm/marvell/ |
| D | armada-380-mpcore-soc-ctrl.txt | 1 Marvell Armada 38x CA9 MPcore SoC Controller
6 - compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
9 datasheet for the CA9 MPcore SoC Control registers
11 mpcore-soc-ctrl@20d20 {
12 compatible = "marvell,armada-380-mpcore-soc-ctrl";
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| D | armada-7k-8k.yaml | 18 - description: Armada 7020 SoC
24 - description: Armada 7040 SoC
30 - description: Armada 8020 SoC
36 - description: Armada 8040 SoC
42 - description: Armada CN9130 SoC with no external CP
48 - description: Armada CN9131 SoC with one external CP
55 - description: Armada CN9132 SoC with two external CPs
|
| /Documentation/sound/soc/ |
| D | platform.rst | 5 An ASoC platform driver class can be divided into audio DMA drivers, SoC DAI
6 drivers and DSP drivers. The platform drivers only target the SoC CPU and must
15 /* SoC audio ops */
51 An example DMA driver is soc/pxa/pxa2xx-pcm.c
54 SoC DAI Drivers
57 Each SoC DAI driver must provide the following features:-
68 SoC DSP Drivers
71 Each SoC DSP driver usually supplies the following features :-
|
| /Documentation/devicetree/bindings/mmc/ |
| D | bluefield-dw-mshc.txt | 1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
20 /* Mellanox Bluefield SoC MMC */
|
| /Documentation/devicetree/bindings/media/ |
| D | mtk-cir.txt | 2 found in Mediatek SoC family
6 "mediatek,mt7623-cir": for MT7623 SoC
7 "mediatek,mt7622-cir": for MT7622 SoC
11 - "clk" entries: for MT7623 SoC
12 - "clk", "bus" entries: for MT7622 SoC
|
| /Documentation/devicetree/bindings/fpga/ |
| D | intel-stratix10-soc-fpga-mgr.txt | 1 Intel Stratix10 SoC FPGA Manager
7 - compatible : should contain "intel,stratix10-soc-fpga-mgr" or
8 "intel,agilex-soc-fpga-mgr"
15 compatible = "intel,stratix10-soc-fpga-mgr";
|
| /Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 3 This node is intended to allow SoC reset in case of software reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
33 begins from 0 to 3, as keystone can contain up to 4 SoC
38 WDT0 is triggered it issues hard reset for SoC.
59 WDT0 or WDT2 is triggered it issues soft reset for SoC.
|