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| /Documentation/arch/x86/x86_64/ |
| D | 5level-paging.rst | 10 space and 64 TiB of physical address space. We are already bumping into
17 It bumps the limits to 128 PiB of virtual address space and 4 PiB of
18 physical address space. This "ought to be enough for anybody" ©.
34 User-space and large virtual address space
36 On x86, 5-level paging enables 56-bit userspace virtual address space.
37 Not all user space is ready to handle wide addresses. It's known that
42 To mitigate this, we are not going to allocate virtual address space
45 But userspace can ask for allocation from full address space by
50 occupied, we look for unmapped area in *full* address space, rather than
58 to allocation from 47-bit address space.
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| D | mm.rst | 13 from the top of the 64-bit address space. It's easier to understand the layout
17 64-bit address space (ffffffffffffffff).
19 Note that as we get closer to the top of the address space, the notation changes
24 It also shows it nicely how incredibly large 64-bit address space is.
32 …0000000000000000 | 0 | 00007fffffffffff | 128 TB | user-space virtual memory, different …
40 … | Kernel-space virtual memory, shared between all processes:
47 ffffc90000000000 | -55 TB | ffffe8ffffffffff | 32 TB | vmalloc/ioremap space (vmalloc_base)
63 ffffffef00000000 | -68 GB | fffffffeffffffff | 64 GB | EFI region mapping space
67 ffffffffa0000000 |-1536 MB | fffffffffeffffff | 1520 MB | module mapping space
80 - With 56-bit addresses, user-space memory gets expanded by a factor of 512x,
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| /Documentation/mm/ |
| D | active_mm.rst | 31 difference is that an anonymous address space doesn't care about the
33 anonymous address space we just leave the previous address space
36 The obvious use for a "anonymous address space" is any thread that
39 some amount of time they are not going to be interested in user space,
44 - "tsk->mm" points to the "real address space". For an anonymous process,
46 really doesn't _have_ a real address space at all.
48 - however, we obviously need to keep track of which address space we
50 which shows what the currently active address space is.
52 The rule is that for a process with a real address space (ie tsk->mm is
58 anonymous process gets scheduled away, the borrowed address space is
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| /Documentation/PCI/ |
| D | acpi-info.rst | 12 method for accessing PCI config space below it, the address space windows
33 reserving address space. The static tables are for things the OS needs to
45 describe all the address space they consume. This includes all the windows
53 space, since it is consumed by the host bridge.
58 spec defines Consumer/Producer only for the Extended Address Space
60 Address Space descriptors. Consequently, OSes have to assume all
63 Prior to the addition of Extended Address Space descriptors, the failure of
66 bridge registers (including ECAM space) in PNP0C02 catch-all devices [6].
67 With the exception of ECAM, the bridge register space is device-specific
71 New architectures should be able to use "Consumer" Extended Address Space
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| /Documentation/powerpc/ |
| D | pci_iov_resource_on_powernv.rst | 57 - For DMA we then provide an entire address space for each PE that can
63 - For MSIs, we have two windows in the address space (one at the top of
64 the 32-bit space and one much higher) which, via a combination of the
75 from the CPU address space to the PCI address space. There is one M32
78 the CPU address space to the PCIe bus and must be naturally aligned
89 portion of address space from the CPU to PCIe
93 ignores that however and will forward in that space if we try).
96 maps each segment to a PE#. That allows portions of the MMIO space
102 onto a segment alignment/granularity so that the space behind a bridge
127 for large BARs in 64-bit space:
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| /Documentation/hwmon/ |
| D | f71882fg.rst | 10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
34 Addresses scanned: none, address read from Super I/O config space
42 Addresses scanned: none, address read from Super I/O config space
50 Addresses scanned: none, address read from Super I/O config space
58 Addresses scanned: none, address read from Super I/O config space
66 Addresses scanned: none, address read from Super I/O config space
74 Addresses scanned: none, address read from Super I/O config space
82 Addresses scanned: none, address read from Super I/O config space
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| D | it87.rst | 10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
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| /Documentation/riscv/ |
| D | vm-layout.rst | 26 occur.": that splits the virtual address space into 2 halves separated by a very
39 …0000000000000000 | 0 | 0000003fffffffff | 256 GB | user-space virtual memory, different …
47 … | Kernel-space virtual memory, shared between all processes:
53 ffffffc800000000 | -224 GB | ffffffd7ffffffff | 64 GB | vmalloc/ioremap space
75 …0000000000000000 | 0 | 00007fffffffffff | 128 TB | user-space virtual memory, different …
83 … | Kernel-space virtual memory, shared between all processes:
89 ffff8f8000000000 | -112.5 TB | ffffaf7fffffffff | 32 TB | vmalloc/ioremap space
111 …0000000000000000 | 0 | 00ffffffffffffff | 64 PB | user-space virtual memory, different …
119 … | Kernel-space virtual memory, shared between all processes:
125 ff20000000000000 | -56 PB | ff5fffffffffffff | 16 PB | vmalloc/ioremap space
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| /Documentation/arch/arm/ |
| D | memory.rst | 14 space, and this must be shared between user space processes, the
18 certain regions of VM space for use for new facilities; therefore
19 this document may reserve more VM space over time.
56 fee00000 feffffff Mapping of PCI I/O space. This is a static
57 mapping within the vmalloc space.
59 VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
74 space.
76 MODULES_VADDR MODULES_END-1 Kernel module space
85 00001000 TASK_SIZE-1 User space mappings
93 space are also caught via this mapping.
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| /Documentation/filesystems/ |
| D | quota.rst | 7 Quota subsystem allows system administrator to set limits on used space and
9 each file or directory) for users and/or groups. For both used space and number
15 more space/inodes until he frees enough of them to get below softlimit.
63 space (block) hardlimit
65 space (block) softlimit is exceeded
68 space (block) softlimit
78 space (block) hardlimit
80 space (block) softlimit
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| D | xfs-delayed-logging-design.rst | 27 are atomic and recoverable. For reasons of space and time efficiency, the
40 The reason for these differences is to keep the amount of log space and CPU time
57 XFS has two types of high level transactions, defined by the type of log space
79 space that was taken at the transaction allocation time.
155 because it can't be written to the journal due to a lack of space in the
160 A transaction reservation provides a guarantee that there is physical log space
165 transaction, we have to reserve enough space to record a full leaf-to-root split
170 free space, which modifies the free space trees. That's two btrees. Inserting
172 btree, which requires another allocation that can modify the free space trees
174 another btree which might require more space. And so on. Hence the amount of
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dcsr.txt | 17 debug blocks defined within this memory space.
25 The DCSR space exists in the memory-mapped bus.
44 range of the DCSR space.
57 This node represents the region of DCSR space allocated to the EPU
91 offset and length of the DCSR space registers of the device
107 This node represents the region of DCSR space allocated to the NPC
120 offset and length of the DCSR space registers of the device
122 The Nexus Port controller occupies two regions in the DCSR space
144 This node represents the region of DCSR space allocated to the NXC
157 offset and length of the DCSR space registers of the device
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| D | ecm.txt | 8 The LAW node represents the region of CCSR space where local access
10 of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
24 physical address offset and length of the CCSR space
37 The E500 LAW node represents the region of CCSR space where ECM config
39 of CCSR space.
53 physical address offset and length of the CCSR space
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| D | mcm.txt | 8 The LAW node represents the region of CCSR space where local access
10 of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
24 physical address offset and length of the CCSR space
37 The MPX LAW node represents the region of CCSR space where MCM config
39 of CCSR space.
53 physical address offset and length of the CCSR space
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| /Documentation/driver-api/media/ |
| D | rc-core.rst | 34 When the carrier is switched off, it is called *SPACE*.
37 *PULSE* and *SPACE* events, each with a given duration.
40 *PULSE* and *SPACE* events depend on the protocol.
42 start with a 9ms *PULSE* and a 4.5ms SPACE. It then transmits 16 bits of
45 with 560µs *PULSE* followed by 1690µs *SPACE* and a bit "0" is modulated
46 with 560µs *PULSE* followed by 560µs *SPACE*.
49 signal in a sequence of *PULSE/SPACE* events, filtering out the carrier
52 of time it receives *PULSE/SPACE* events.
57 microcontroller that decode the *PULSE/SPACE* sequence and return scan
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| /Documentation/driver-api/ |
| D | zorro.rst | 17 - The Zorro II address space is 24-bit and lies within the first 16 MB of the
21 with Zorro II. The Zorro III address space lies outside the first 16 MB.
57 not yet in use. This is done using the I/O memory space resource management
63 Shortcuts to claim the whole device's address space are provided as well::
69 Accessing the Zorro Address Space
76 The treatment of these regions depends on the type of Zorro space:
78 - Zorro II address space is always mapped and does not have to be mapped
87 - Zorro III address space must be mapped explicitly using z_ioremap() first
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| D | ptp.rst | 9 presents a standardized method for developing PTP user space
14 drivers and a user space interface. The infrastructure supports a
25 - Period output signals configurable from user space
26 - Low Pass Filter (LPF) access from user space
33 class driver handles all of the dealings with user space. The
44 PTP hardware clock user space API
48 registered clock. User space can use an open file descriptor from
53 User space programs may control the clock using standardized
55 ancillary clock features. User space can receive time stamped
124 … - Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)
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| /Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie.yaml | 41 At least DBI reg-space and peripheral devices CFG-space outbound window
43 also required if the space is unrolled (IP-core version >= 4.80a).
53 Basic DWC PCIe controller configuration-space accessible over
54 the DBI interface. This memory space is either activated with
61 Shadow DWC PCIe config-space registers. This space is selected
63 the PCI-SIG PCIe CFG-space with the shadow registers for some
64 PCI Header space, PCI Standard and Extended Structures. It's
71 registers normally defined by the platform engineers. The space
78 unrolled memory space with the internal Address Translation
82 set of viewport CSRs mapped into the PL space. Note iATU is
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| D | snps,dw-pcie-ep.yaml | 34 if the space is unrolled (IP-core version >= 4.80a).
44 Basic DWC PCIe controller configuration-space accessible over
45 the DBI interface. This memory space is either activated with
52 Shadow DWC PCIe config-space registers. This space is selected
54 the PCI-SIG PCIe CFG-space with the shadow registers for some
55 PCI Header space, PCI Standard and Extended Structures. It's
62 registers normally defined by the platform engineers. The space
69 unrolled memory space with the internal Address Translation
73 set of viewport CSRs mapped into the PL space. Note iATU is
177 <0xd0000000 0x2000000>; /* Configuration space */
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| /Documentation/virt/kvm/devices/ |
| D | vm.rst | 63 Allows user space to retrieve machine and kvm specific cpu related information::
75 :Returns: -EFAULT if the given address is not accessible from kernel space;
82 Allows user space to retrieve or request to change cpu related information for a vcpu::
100 -EFAULT if the given address is not accessible from kernel space;
109 Allows user space to retrieve available cpu features. A feature is available if
120 :Returns: -EFAULT if the given address is not accessible from kernel space;
126 Allows user space to retrieve or change enabled cpu features for all VCPUs of a
133 :Returns: -EFAULT if the given address is not accessible from kernel space;
143 Allows user space to retrieve available cpu subfunctions without any filtering
176 :Returns: -EFAULT if the given address is not accessible from kernel space;
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| /Documentation/firmware-guide/acpi/ |
| D | video_extension.rst | 16 Export a sysfs interface for user space to control backlight level
70 as a "brightness level" indicator. Thus from the user space perspective
74 Notify user space about hotkey event
80 generated and sent to user space through the input device created by
82 following key code will appear to user space::
95 notify value it received and send the event to user space through the
108 Once user space tool receives this event, it can modify the backlight
116 not affect the sending of event to user space, they are always sent to user
117 space regardless of whether or not the video module controls the backlight level
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| /Documentation/crypto/ |
| D | userspace-if.rst | 1 User Space Interface
7 The concepts of the kernel crypto API visible to kernel space is fully
8 applicable to the user space interface as well. Therefore, the kernel
12 The major difference, however, is that user space can only act as a
16 The following covers the user space interface exported by the kernel
18 be obtained from [1]. That library can be used by user space
22 user space, however. This includes the difference between synchronous
23 and asynchronous invocations. The user space API call is fully
28 User Space API General Remarks
31 The kernel crypto API is accessible from user space. Currently, the
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| /Documentation/RCU/Design/Data-Structures/ |
| D | HugeTreeClassicRCU.svg | 472 xml:space="preserve"
484 xml:space="preserve"
496 xml:space="preserve"
508 xml:space="preserve"
520 xml:space="preserve"
532 xml:space="preserve"
544 xml:space="preserve"
556 xml:space="preserve"
568 xml:space="preserve"
580 xml:space="preserve"
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| /Documentation/mm/damon/ |
| D | design.rst | 14 the given monitoring target address-space and available set of
19 interfaces for the user space, on top of the core layer.
27 the given target address space. On the other hand, the accuracy and overhead
29 space. DAMON separates the two parts in different layers, namely DAMON
34 Due to this design, users can extend DAMON for any address space by configuring
38 For example, physical memory, virtual memory, swap space, those for specific
48 programming interface to all kernel space components such as subsystems and
51 used by the user space end users.
59 1. Identification of the monitoring target address range for the address space.
60 2. Access check of specific address range in the target space.
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| D | faq.rst | 10 No. The core of the DAMON is address space independent. The address space
14 space with any access check technique.
17 implementations of the address space dependent functions for the virtual memory
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