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/drivers/staging/media/atomisp/pci/
Dia_css_isp_params.c72 const struct ia_css_pipeline_stage *stage, in ia_css_process_aa() argument
76 stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; in ia_css_process_aa()
78 stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; in ia_css_process_aa()
82 … &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; in ia_css_process_aa()
92 const struct ia_css_pipeline_stage *stage, in ia_css_process_anr() argument
99 stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; in ia_css_process_anr()
102 stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; in ia_css_process_anr()
109 &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], in ia_css_process_anr()
113 params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = in ia_css_process_anr()
127 const struct ia_css_pipeline_stage *stage, in ia_css_process_anr2() argument
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Dsh_css_sp.c124 unsigned int stage) in store_sp_stage_data() argument
132 sh_css_store_isp_stage_to_ddr(pipe_num, stage); in store_sp_stage_data()
133 sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = in store_sp_stage_data()
134 sh_css_store_sp_stage_to_ddr(pipe_num, stage); in store_sp_stage_data()
806 is_sp_stage(struct ia_css_pipeline_stage *stage) in is_sp_stage() argument
808 assert(stage); in is_sp_stage()
809 return stage->sp_func != IA_CSS_PIPELINE_NO_FUNC; in is_sp_stage()
914 unsigned int stage, in sh_css_sp_init_stage() argument
952 sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = mmgr_NULL; in sh_css_sp_init_stage()
959 sh_css_sp_stage.deinterleaved = ((stage == 0) && continuous); in sh_css_sp_init_stage()
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/drivers/staging/media/atomisp/pci/runtime/pipeline/src/
Dpipeline.c49 static void pipeline_stage_destroy(struct ia_css_pipeline_stage *stage);
260 /* @brief Add a stage to pipeline.
263 * @param[in] stage_desc The description of the stage
264 * @param[out] stage The successor of the stage.
267 * Add a new stage to a non-NULL pipeline.
268 * The stage consists of an ISP binary or firmware and input and
274 struct ia_css_pipeline_stage **stage) in ia_css_pipeline_create_and_add_stage() argument
294 /* Find the last stage */ in ia_css_pipeline_create_and_add_stage()
299 * stage, if no previous stage, it's an error. in ia_css_pipeline_create_and_add_stage()
313 /* Create the new stage */ in ia_css_pipeline_create_and_add_stage()
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/drivers/thermal/qcom/
Dqcom-spmi-temp-alarm.c66 /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
76 unsigned int stage; member
79 /* protects .thresh, .stage and chip registers */
87 /* This array maps from GEN2 alarm state to GEN1 alarm stage */
110 * specified over-temperature stage
112 * @stage: Over-temperature stage
116 static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) in qpnp_tm_decode_temp() argument
118 if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || in qpnp_tm_decode_temp()
119 stage > STAGE_COUNT) in qpnp_tm_decode_temp()
122 return (*chip->temp_map)[chip->thresh][stage - 1]; in qpnp_tm_decode_temp()
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/drivers/staging/media/atomisp/pci/runtime/pipeline/interface/
Dia_css_pipeline.h25 /* Pipeline stage to be executed on SP/ISP */
31 /* SP function for SP stage */
42 /* Pipeline of n stages to be executed on SP/ISP per stage */
69 /* Stage descriptor used to create a new stage in the pipeline */
149 /* @brief Add a stage to pipeline.
152 * @param[in] stage_desc The description of the stage
153 * @param[out] stage The successor of the stage.
156 * Add a new stage to a non-NULL pipeline.
157 * The stage consists of an ISP binary or firmware and input and output
163 struct ia_css_pipeline_stage **stage);
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/drivers/watchdog/
Dkempld_wdt.c10 * First the pretimeout stage runs out before the timeout stage gets
77 struct kempld_wdt_stage stage[KEMPLD_WDT_MAX_STAGES]; member
103 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_action() argument
109 if (!stage || !stage->mask) in kempld_wdt_set_stage_action()
113 stage_cfg = kempld_read8(pld, KEMPLD_WDT_STAGE_CFG(stage->id)); in kempld_wdt_set_stage_action()
122 kempld_write8(pld, KEMPLD_WDT_STAGE_CFG(stage->id), stage_cfg); in kempld_wdt_set_stage_action()
129 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_timeout() argument
141 if (!stage) in kempld_wdt_set_stage_timeout()
149 if (stage_timeout64 > stage->mask) in kempld_wdt_set_stage_timeout()
152 stage_timeout = stage_timeout64 & stage->mask; in kempld_wdt_set_stage_timeout()
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Dsbsa_gwdt.c11 * ARM SBSA Generic Watchdog has two stage timeouts:
17 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
19 * In the single stage mode, when the timeout is reached, your system
24 * second stage (as long as the first stage) will be reached, system will be
33 * if action is 0 (the single stage mode):
37 * Note: Since this watchdog timer has two stages, and each stage is determined
38 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
40 * is half of that in the single stage mode.
158 * In the single stage mode, The first signal (WS0) is ignored, in sbsa_gwdt_set_timeout()
173 * In the single stage mode, if WS0 is deasserted in sbsa_gwdt_get_timeleft()
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/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_lm.c18 /* These register are offset to mixer base + stage base */
35 * for the stage to be setup
37 * @stage: stage index to setup
39 static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) in _stage_offset() argument
42 if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages) in _stage_offset()
43 return sblk->blendstage_base[stage - DPU_STAGE_0]; in _stage_offset()
95 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) in dpu_hw_lm_setup_blend_config_combined_alpha() argument
101 if (stage == DPU_STAGE_BASE) in dpu_hw_lm_setup_blend_config_combined_alpha()
104 stage_off = _stage_offset(ctx, stage); in dpu_hw_lm_setup_blend_config_combined_alpha()
114 u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) in dpu_hw_lm_setup_blend_config() argument
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/drivers/net/ethernet/microchip/vcap/
Dvcap_api.h17 #define VCAP_CID_INGRESS_L0 1000000 /* Ingress Stage 1 Lookup 0 */
18 #define VCAP_CID_INGRESS_L1 1100000 /* Ingress Stage 1 Lookup 1 */
19 #define VCAP_CID_INGRESS_L2 1200000 /* Ingress Stage 1 Lookup 2 */
20 #define VCAP_CID_INGRESS_L3 1300000 /* Ingress Stage 1 Lookup 3 */
21 #define VCAP_CID_INGRESS_L4 1400000 /* Ingress Stage 1 Lookup 4 */
22 #define VCAP_CID_INGRESS_L5 1500000 /* Ingress Stage 1 Lookup 5 */
24 #define VCAP_CID_PREROUTING_IPV6 3000000 /* Prerouting Stage */
25 #define VCAP_CID_PREROUTING 6000000 /* Prerouting Stage */
27 #define VCAP_CID_INGRESS_STAGE2_L0 8000000 /* Ingress Stage 2 Lookup 0 */
28 #define VCAP_CID_INGRESS_STAGE2_L1 8100000 /* Ingress Stage 2 Lookup 1 */
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/drivers/net/wwan/iosm/
Diosm_ipc_mmio.c22 /* CP execution stage */
47 * execution stage into mmio area
51 /* check if exec stage has one of the valid values */
52 static bool ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage) in ipc_mmio_is_valid_exec_stage() argument
54 switch (stage) { in ipc_mmio_is_valid_exec_stage()
87 enum ipc_mem_exec_stage stage; in ipc_mmio_init() local
98 /* Check for a valid execution stage to make sure that the boot code in ipc_mmio_init()
102 stage = ipc_mmio_get_exec_stage(ipc_mmio); in ipc_mmio_init()
103 if (ipc_mmio_is_valid_exec_stage(stage)) in ipc_mmio_init()
110 dev_err(ipc_mmio->dev, "invalid exec stage %X", stage); in ipc_mmio_init()
/drivers/net/wireless/broadcom/b43/
Dphy_n.h340 #define B43_NPHY_TXF_20CO_AS0 B43_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */
341 #define B43_NPHY_TXF_20CO_AS1 B43_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */
342 #define B43_NPHY_TXF_20CO_AS2 B43_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */
343 #define B43_NPHY_TXF_20CO_B32S0 B43_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */
344 #define B43_NPHY_TXF_20CO_B1S0 B43_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */
345 #define B43_NPHY_TXF_20CO_B32S1 B43_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */
346 #define B43_NPHY_TXF_20CO_B1S1 B43_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */
347 #define B43_NPHY_TXF_20CO_B32S2 B43_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */
348 #define B43_NPHY_TXF_20CO_B1S2 B43_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */
364 #define B43_NPHY_TXF_40CO_AS0 B43_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */
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/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_ctl.c289 enum mdp_mixer_stage_id stage) in mdp_ctl_blend_mask() argument
292 case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage); in mdp_ctl_blend_mask()
293 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
294 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
295 case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage); in mdp_ctl_blend_mask()
296 case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage); in mdp_ctl_blend_mask()
297 case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage); in mdp_ctl_blend_mask()
298 case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage); in mdp_ctl_blend_mask()
299 case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage); in mdp_ctl_blend_mask()
300 case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage); in mdp_ctl_blend_mask()
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Dmdp5_ctl.h46 * @stage: array to contain the pipe num for each stage
47 * @stage_cnt: valid stage number in stage array
56 enum mdp5_pipe stage[][MAX_PIPE_STAGE],
Dmdp5_crtc.c185 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage) in mdp5_lm_use_fg_alpha_mask() argument
187 switch (stage) { in mdp5_lm_use_fg_alpha_mask()
201 * left/right pipe offsets for the stage array used in blend_setup()
210 * Otherwise all layers will be blended based on their stage calculated
229 enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; in blend_setup() enum
235 #define blender(stage) ((stage) - STAGE0) in blend_setup() argument
252 pstates[pstate->stage] = pstate; in blend_setup()
253 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane); in blend_setup()
255 * if we have a right mixer, stage the same pipe as we in blend_setup()
259 r_stage[pstate->stage][PIPE_LEFT] = in blend_setup()
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/drivers/gpu/drm/ci/
Dtest.yml88 stage: msm
102 stage: msm
121 stage: msm
134 stage: msm
147 stage: rockchip
160 stage: rockchip
174 stage: i915
247 stage: amdgpu
266 stage: mediatek
307 stage: meson
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/drivers/staging/media/atomisp/pci/camera/pipe/interface/
Dia_css_pipe_binarydesc.h68 /* @brief Get a binary descriptor for preview stage.
87 /* @brief Get a binary descriptor for video stage.
106 /* @brief Get a binary descriptor for yuv scaler stage.
125 /* @brief Get a binary descriptor for capture pp stage.
159 /* @brief Get a binary descriptor for pre gdc stage.
174 /* @brief Get a binary descriptor for gdc stage.
221 /* @brief Get a binary descriptor for pre anr stage.
236 /* @brief Get a binary descriptor for ANR stage.
251 /* @brief Get a binary descriptor for post anr stage.
268 /* @brief Get a binary descriptor for ldc stage.
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_kms.h96 enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage) in mixercfg() argument
102 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) | in mixercfg()
108 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) | in mixercfg()
114 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) | in mixercfg()
120 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) | in mixercfg()
126 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) | in mixercfg()
132 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) | in mixercfg()
138 mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) | in mixercfg()
/drivers/media/radio/wl128x/
Dfmdrv_common.c173 fmdev->irq_info.handlers[fmdev->irq_info.stage](fmdev); in fm_irq_call()
177 static inline void fm_irq_call_stage(struct fmdev *fmdev, u8 stage) in fm_irq_call_stage() argument
179 fmdev->irq_info.stage = stage; in fm_irq_call_stage()
183 static inline void fm_irq_timeout_stage(struct fmdev *fmdev, u8 stage) in fm_irq_timeout_stage() argument
185 fmdev->irq_info.stage = stage; in fm_irq_timeout_stage()
279 if (irq_info->stage != 0) { in recv_tasklet()
280 fmerr("Inval stage resetting to zero\n"); in recv_tasklet()
281 irq_info->stage = 0; in recv_tasklet()
288 irq_info->handlers[irq_info->stage](fmdev); in recv_tasklet()
315 irq_info->handlers[irq_info->stage](fmdev); in recv_tasklet()
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/drivers/usb/renesas_usbhs/
Dcommon.h142 #define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
158 #define CTRT (1 << 11) /* Control Stage Interrupt Status */
171 #define CTSQ_MASK (0x7) /* Control Transfer Stage */
172 #define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
173 #define READ_DATA_STAGE 1 /* Control read data stage */
174 #define READ_STATUS_STAGE 2 /* Control read status stage */
175 #define WRITE_DATA_STAGE 3 /* Control write data stage */
176 #define WRITE_STATUS_STAGE 4 /* Control write status stage */
177 #define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
/drivers/input/misc/
Dkeyspan_remote.c117 int stage; member
185 switch(remote->stage) { in keyspan_check_data()
188 * In stage 0 we want to find the start of a message. The remote sends a 0xFF as filler. in keyspan_check_data()
199 remote->stage = 1; in keyspan_check_data()
205 * Stage 1 we should have 16 bytes and should be able to detect a in keyspan_check_data()
215 remote->stage = 0; in keyspan_check_data()
232 remote->stage = 0; in keyspan_check_data()
235 remote->stage = 2; in keyspan_check_data()
241 * Stage 2 we should have 24 bytes which will be enough for a full in keyspan_check_data()
264 remote->stage = 0; in keyspan_check_data()
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/drivers/net/ipa/
Dipa.h74 * @setup_complete: Flag indicating whether setup stage has completed
147 * Activities performed at the init stage can be done without requiring
148 * any access to IPA hardware. Activities performed at the config stage
150 * The setup stage is performed only after the GSI hardware is ready
151 * (more on this below). The setup stage allows the AP to perform
155 * This function, @ipa_setup(), starts the setup stage.
/drivers/usb/gadget/udc/
Dgr_udc.h179 GR_EP0_IDATA, /* IN data stage */
180 GR_EP0_ODATA, /* OUT data stage */
181 GR_EP0_ISTATUS, /* Status stage after IN data stage */
182 GR_EP0_OSTATUS, /* Status stage after OUT data stage */
/drivers/gpu/drm/tiny/
Drepaper.c202 enum repaper_stage stage) in repaper_even_pixels() argument
217 switch (stage) { in repaper_even_pixels()
248 enum repaper_stage stage) in repaper_odd_pixels() argument
262 switch (stage) { in repaper_odd_pixels()
298 enum repaper_stage stage) in repaper_all_pixels() argument
314 switch (stage) { in repaper_all_pixels()
342 enum repaper_stage stage) in repaper_one_line() argument
354 repaper_odd_pixels(epd, &p, data, fixed_value, mask, stage); in repaper_one_line()
365 repaper_even_pixels(epd, &p, data, fixed_value, mask, stage); in repaper_one_line()
379 repaper_all_pixels(epd, &p, data, fixed_value, mask, stage); in repaper_one_line()
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/drivers/net/dsa/sja1105/
Dsja1105_clocking.c401 pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */ in sja1105_rgmii_cfg_pad_tx_config()
403 pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */ in sja1105_rgmii_cfg_pad_tx_config()
405 pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */ in sja1105_rgmii_cfg_pad_tx_config()
407 pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */ in sja1105_rgmii_cfg_pad_tx_config()
409 pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */ in sja1105_rgmii_cfg_pad_tx_config()
410 pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
411 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ in sja1105_rgmii_cfg_pad_tx_config()
413 pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
430 pad_mii_rx.d32_ih = 0; /* RXD[3:2] input stage hysteresis: */ in sja1105_cfg_pad_rx_config()
434 pad_mii_rx.d10_ih = 0; /* RXD[1:0] input stage hysteresis: */ in sja1105_cfg_pad_rx_config()
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/drivers/media/test-drivers/vicodec/
Dcodec-fwht.c259 /* stage 1 */ in fwht()
316 /* stage 2 */ in fwht()
327 /* stage 3 */ in fwht()
341 /* stage 1 */ in fwht()
354 /* stage 2 */ in fwht()
364 /* stage 3 */ in fwht()
392 /* stage 1 */ in fwht16()
405 /* stage 2 */ in fwht16()
416 /* stage 3 */ in fwht16()
430 /* stage 1 */ in fwht16()
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