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/Documentation/devicetree/bindings/spi/
Dnvidia,tegra210-quad-peripheral-props.yaml17 Tap value varies based on platform design trace lengths from Tegra
26 Tap value varies based on platform design trace lengths from Tegra
/Documentation/devicetree/bindings/gpio/
Dnvidia,tegra186-gpio.yaml28 features available, varies between the different GPIO controllers.
47 The number of ports implemented by each GPIO controller varies. The number
48 of implemented GPIOs within each port varies. GPIO registers within a
63 varies as a rough function of the number of ports it implements. Note
110 required varies depending on compatible value.
/Documentation/sound/soc/
Ddai.rst30 usually varies depending on the sample rate and the master system clock
53 receive the audio data. Bit clock usually varies depending on sample rate
/Documentation/ABI/testing/
Dsysfs-class-leds-gt683r18 Breathing: LEDs brightness varies at human breathing rate
Dsysfs-class-mei29 Also number of registers varies between 1 and 6
/Documentation/devicetree/bindings/net/
Dcavium-pip.txt41 Value range is 1-31, and mapping to the actual delay varies depending on HW.
44 Value range is 1-31, and mapping to the actual delay varies depending on HW.
/Documentation/devicetree/bindings/watchdog/
Dcdns,wdt-r1p2.yaml15 a programmable reset period. The timeout period varies from 1 ms
/Documentation/devicetree/bindings/mtd/partitions/
Dqcom,smem-part.yaml15 varies between partition table revisions. V3 supports maximum 16 partitions
/Documentation/userspace-api/media/dvb/
Dfe-read-status.rst43 varies according with the architecture. This needs to be fixed in the
/Documentation/rust/
Darch-support.rst8 support for building the kernel with LLVM/Clang varies (please see
/Documentation/devicetree/bindings/pinctrl/
Dbrcm,ns-pinmux.yaml18 A list of pins varies across chipsets so few bindings are available.
Dmediatek,mt8192-pinctrl.yaml74 Supported pin number and mux varies for different SoCs, and are
Dmediatek,mt65xx-pinctrl.yaml92 Supported pin number and mux varies for different SoCs, and are
/Documentation/arch/arm64/
Dhugetlbpage.rst31 pte (last) level. The number of supported contiguous entries varies by page size
/Documentation/input/devices/
Diforce-protocol.rst63 LEN= Varies from device to device
80 LEN= Varies
218 Query command. Length varies according to the query type.
/Documentation/devicetree/bindings/phy/
Dnvidia,tegra194-xusb-padctl.yaml400 valid port numbers varies with the SoC generation.
433 valid port numbers varies with the SoC generation.
466 valid port numbers varies with the SoC generation.
499 valid port numbers varies with the SoC generation.
Dnvidia,tegra186-xusb-padctl.yaml363 valid port numbers varies with the SoC generation.
384 valid port numbers varies with the SoC generation.
405 valid port numbers varies with the SoC generation.
Dnvidia,tegra210-xusb-padctl.yaml532 valid port numbers varies with the SoC generation.
553 valid port numbers varies with the SoC generation.
574 valid port numbers varies with the SoC generation.
595 valid port numbers varies with the SoC generation.
/Documentation/misc-devices/
Dapds990x.rst68 to saturate much before that. Real max value varies depending
/Documentation/devicetree/bindings/input/
Datmel,maxtouch.yaml61 Note: the numbering of the GPIOs and the bit they start at varies
/Documentation/hwmon/
Dfam15h_power.rst28 processor varies based on the workload being executed. Derated power
Dmax31827.rst72 the conversion frequency to 1 conv/s. The conversion time varies depending on
/Documentation/devicetree/bindings/opp/
Dallwinner,sun50i-h6-operating-points.yaml15 OPP varies based on the silicon variant in use. Allwinner Process
/Documentation/timers/
Dtimers-howto.rst59 driving each of these calls varies, thus there are
/Documentation/devicetree/bindings/display/rockchip/
Drockchip,dw-hdmi.yaml34 varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes

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