1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DPIO_PHY_H__ 7 #define __INTEL_DPIO_PHY_H__ 8 9 #include <linux/types.h> 10 11 enum pipe; 12 enum port; 13 struct drm_i915_private; 14 struct intel_crtc_state; 15 struct intel_digital_port; 16 struct intel_encoder; 17 18 enum dpio_channel { 19 DPIO_CH0, 20 DPIO_CH1, 21 }; 22 23 enum dpio_phy { 24 DPIO_PHY0, 25 DPIO_PHY1, 26 DPIO_PHY2, 27 }; 28 29 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, 30 enum dpio_phy *phy, enum dpio_channel *ch); 31 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, 32 const struct intel_crtc_state *crtc_state); 33 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); 34 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); 35 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 36 enum dpio_phy phy); 37 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 38 enum dpio_phy phy); 39 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count); 40 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, 41 u8 lane_lat_optim_mask); 42 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); 43 44 enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port); 45 enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port); 46 enum dpio_channel vlv_pipe_to_channel(enum pipe pipe); 47 48 void chv_set_phy_signal_level(struct intel_encoder *encoder, 49 const struct intel_crtc_state *crtc_state, 50 u32 deemph_reg_value, u32 margin_reg_value, 51 bool uniq_trans_scale); 52 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 53 const struct intel_crtc_state *crtc_state, 54 bool reset); 55 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 56 const struct intel_crtc_state *crtc_state); 57 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 58 const struct intel_crtc_state *crtc_state); 59 void chv_phy_release_cl2_override(struct intel_encoder *encoder); 60 void chv_phy_post_pll_disable(struct intel_encoder *encoder, 61 const struct intel_crtc_state *old_crtc_state); 62 63 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 64 const struct intel_crtc_state *crtc_state, 65 u32 demph_reg_value, u32 preemph_reg_value, 66 u32 uniqtranscale_reg_value, u32 tx3_demph); 67 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 68 const struct intel_crtc_state *crtc_state); 69 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 70 const struct intel_crtc_state *crtc_state); 71 void vlv_phy_reset_lanes(struct intel_encoder *encoder, 72 const struct intel_crtc_state *old_crtc_state); 73 74 #endif /* __INTEL_DPIO_PHY_H__ */ 75