1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35 #define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
36
37 struct clk;
38 struct clk_hw;
39 struct clk_core;
40 struct dentry;
41
42 /**
43 * struct clk_rate_request - Structure encoding the clk constraints that
44 * a clock user might require.
45 *
46 * Should be initialized by calling clk_hw_init_rate_request().
47 *
48 * @core: Pointer to the struct clk_core affected by this request
49 * @rate: Requested clock rate. This field will be adjusted by
50 * clock drivers according to hardware capabilities.
51 * @min_rate: Minimum rate imposed by clk users.
52 * @max_rate: Maximum rate imposed by clk users.
53 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
54 * requested constraints.
55 * @best_parent_hw: The most appropriate parent clock that fulfills the
56 * requested constraints.
57 *
58 */
59 struct clk_rate_request {
60 struct clk_core *core;
61 unsigned long rate;
62 unsigned long min_rate;
63 unsigned long max_rate;
64 unsigned long best_parent_rate;
65 struct clk_hw *best_parent_hw;
66 };
67
68 void clk_hw_init_rate_request(const struct clk_hw *hw,
69 struct clk_rate_request *req,
70 unsigned long rate);
71 void clk_hw_forward_rate_request(const struct clk_hw *core,
72 const struct clk_rate_request *old_req,
73 const struct clk_hw *parent,
74 struct clk_rate_request *req,
75 unsigned long parent_rate);
76
77 /**
78 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
79 *
80 * @num: Numerator of the duty cycle ratio
81 * @den: Denominator of the duty cycle ratio
82 */
83 struct clk_duty {
84 unsigned int num;
85 unsigned int den;
86 };
87
88 /**
89 * struct clk_ops - Callback operations for hardware clocks; these are to
90 * be provided by the clock implementation, and will be called by drivers
91 * through the clk_* api.
92 *
93 * @prepare: Prepare the clock for enabling. This must not return until
94 * the clock is fully prepared, and it's safe to call clk_enable.
95 * This callback is intended to allow clock implementations to
96 * do any initialisation that may sleep. Called with
97 * prepare_lock held.
98 *
99 * @unprepare: Release the clock from its prepared state. This will typically
100 * undo any work done in the @prepare callback. Called with
101 * prepare_lock held.
102 *
103 * @is_prepared: Queries the hardware to determine if the clock is prepared.
104 * This function is allowed to sleep. Optional, if this op is not
105 * set then the prepare count will be used.
106 *
107 * @unprepare_unused: Unprepare the clock atomically. Only called from
108 * clk_disable_unused for prepare clocks with special needs.
109 * Called with prepare mutex held. This function may sleep.
110 *
111 * @enable: Enable the clock atomically. This must not return until the
112 * clock is generating a valid clock signal, usable by consumer
113 * devices. Called with enable_lock held. This function must not
114 * sleep.
115 *
116 * @disable: Disable the clock atomically. Called with enable_lock held.
117 * This function must not sleep.
118 *
119 * @is_enabled: Queries the hardware to determine if the clock is enabled.
120 * This function must not sleep. Optional, if this op is not
121 * set then the enable count will be used.
122 *
123 * @disable_unused: Disable the clock atomically. Only called from
124 * clk_disable_unused for gate clocks with special needs.
125 * Called with enable_lock held. This function must not
126 * sleep.
127 *
128 * @save_context: Save the context of the clock in prepration for poweroff.
129 *
130 * @restore_context: Restore the context of the clock after a restoration
131 * of power.
132 *
133 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
134 * parent rate is an input parameter. It is up to the caller to
135 * ensure that the prepare_mutex is held across this call. If the
136 * driver cannot figure out a rate for this clock, it must return
137 * 0. Returns the calculated rate. Optional, but recommended - if
138 * this op is not set then clock rate will be initialized to 0.
139 *
140 * @round_rate: Given a target rate as input, returns the closest rate actually
141 * supported by the clock. The parent rate is an input/output
142 * parameter.
143 *
144 * @determine_rate: Given a target rate as input, returns the closest rate
145 * actually supported by the clock, and optionally the parent clock
146 * that should be used to provide the clock rate.
147 *
148 * @set_parent: Change the input source of this clock; for clocks with multiple
149 * possible parents specify a new parent by passing in the index
150 * as a u8 corresponding to the parent in either the .parent_names
151 * or .parents arrays. This function in affect translates an
152 * array index into the value programmed into the hardware.
153 * Returns 0 on success, -EERROR otherwise.
154 *
155 * @get_parent: Queries the hardware to determine the parent of a clock. The
156 * return value is a u8 which specifies the index corresponding to
157 * the parent clock. This index can be applied to either the
158 * .parent_names or .parents arrays. In short, this function
159 * translates the parent value read from hardware into an array
160 * index. Currently only called when the clock is initialized by
161 * __clk_init. This callback is mandatory for clocks with
162 * multiple parents. It is optional (and unnecessary) for clocks
163 * with 0 or 1 parents.
164 *
165 * @set_rate: Change the rate of this clock. The requested rate is specified
166 * by the second argument, which should typically be the return
167 * of .round_rate call. The third argument gives the parent rate
168 * which is likely helpful for most .set_rate implementation.
169 * Returns 0 on success, -EERROR otherwise.
170 *
171 * @set_rate_and_parent: Change the rate and the parent of this clock. The
172 * requested rate is specified by the second argument, which
173 * should typically be the return of .round_rate call. The
174 * third argument gives the parent rate which is likely helpful
175 * for most .set_rate_and_parent implementation. The fourth
176 * argument gives the parent index. This callback is optional (and
177 * unnecessary) for clocks with 0 or 1 parents as well as
178 * for clocks that can tolerate switching the rate and the parent
179 * separately via calls to .set_parent and .set_rate.
180 * Returns 0 on success, -EERROR otherwise.
181 *
182 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
183 * is expressed in ppb (parts per billion). The parent accuracy is
184 * an input parameter.
185 * Returns the calculated accuracy. Optional - if this op is not
186 * set then clock accuracy will be initialized to parent accuracy
187 * or 0 (perfect clock) if clock has no parent.
188 *
189 * @get_phase: Queries the hardware to get the current phase of a clock.
190 * Returned values are 0-359 degrees on success, negative
191 * error codes on failure.
192 *
193 * @set_phase: Shift the phase this clock signal in degrees specified
194 * by the second argument. Valid values for degrees are
195 * 0-359. Return 0 on success, otherwise -EERROR.
196 *
197 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
198 * of a clock. Returned values denominator cannot be 0 and must be
199 * superior or equal to the numerator.
200 *
201 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
202 * the numerator (2nd argurment) and denominator (3rd argument).
203 * Argument must be a valid ratio (denominator > 0
204 * and >= numerator) Return 0 on success, otherwise -EERROR.
205 *
206 * @init: Perform platform-specific initialization magic.
207 * This is not used by any of the basic clock types.
208 * This callback exist for HW which needs to perform some
209 * initialisation magic for CCF to get an accurate view of the
210 * clock. It may also be used dynamic resource allocation is
211 * required. It shall not used to deal with clock parameters,
212 * such as rate or parents.
213 * Returns 0 on success, -EERROR otherwise.
214 *
215 * @terminate: Free any resource allocated by init.
216 *
217 * @debug_init: Set up type-specific debugfs entries for this clock. This
218 * is called once, after the debugfs directory entry for this
219 * clock has been created. The dentry pointer representing that
220 * directory is provided as an argument. Called with
221 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
222 *
223 * @pre_rate_change: Optional callback for a clock to fulfill its rate
224 * change requirements before any rate change has occurred in
225 * its clock tree. Returns 0 on success, -EERROR otherwise.
226 *
227 * @post_rate_change: Optional callback for a clock to clean up any
228 * requirements that were needed while the clock and its tree
229 * was changing states. Returns 0 on success, -EERROR otherwise.
230 *
231 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
232 * implementations to split any work between atomic (enable) and sleepable
233 * (prepare) contexts. If enabling a clock requires code that might sleep,
234 * this must be done in clk_prepare. Clock enable code that will never be
235 * called in a sleepable context may be implemented in clk_enable.
236 *
237 * Typically, drivers will call clk_prepare when a clock may be needed later
238 * (eg. when a device is opened), and clk_enable when the clock is actually
239 * required (eg. from an interrupt). Note that clk_prepare MUST have been
240 * called before clk_enable.
241 */
242 struct clk_ops {
243 int (*prepare)(struct clk_hw *hw);
244 void (*unprepare)(struct clk_hw *hw);
245 int (*is_prepared)(struct clk_hw *hw);
246 void (*unprepare_unused)(struct clk_hw *hw);
247 int (*enable)(struct clk_hw *hw);
248 void (*disable)(struct clk_hw *hw);
249 int (*is_enabled)(struct clk_hw *hw);
250 void (*disable_unused)(struct clk_hw *hw);
251 int (*save_context)(struct clk_hw *hw);
252 void (*restore_context)(struct clk_hw *hw);
253 unsigned long (*recalc_rate)(struct clk_hw *hw,
254 unsigned long parent_rate);
255 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
256 unsigned long *parent_rate);
257 int (*determine_rate)(struct clk_hw *hw,
258 struct clk_rate_request *req);
259 int (*set_parent)(struct clk_hw *hw, u8 index);
260 u8 (*get_parent)(struct clk_hw *hw);
261 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
262 unsigned long parent_rate);
263 int (*set_rate_and_parent)(struct clk_hw *hw,
264 unsigned long rate,
265 unsigned long parent_rate, u8 index);
266 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
267 unsigned long parent_accuracy);
268 int (*get_phase)(struct clk_hw *hw);
269 int (*set_phase)(struct clk_hw *hw, int degrees);
270 int (*get_duty_cycle)(struct clk_hw *hw,
271 struct clk_duty *duty);
272 int (*set_duty_cycle)(struct clk_hw *hw,
273 struct clk_duty *duty);
274 int (*init)(struct clk_hw *hw);
275 void (*terminate)(struct clk_hw *hw);
276 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
277 int (*pre_rate_change)(struct clk_hw *hw,
278 unsigned long rate,
279 unsigned long new_rate);
280 int (*post_rate_change)(struct clk_hw *hw,
281 unsigned long old_rate,
282 unsigned long rate);
283 };
284
285 /**
286 * struct clk_parent_data - clk parent information
287 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
288 * @fw_name: parent name local to provider registering clk
289 * @name: globally unique parent name (used as a fallback)
290 * @index: parent index local to provider registering clk (if @fw_name absent)
291 */
292 struct clk_parent_data {
293 const struct clk_hw *hw;
294 const char *fw_name;
295 const char *name;
296 int index;
297 };
298
299 /**
300 * struct clk_init_data - holds init data that's common to all clocks and is
301 * shared between the clock provider and the common clock framework.
302 *
303 * @name: clock name
304 * @ops: operations this clock supports
305 * @parent_names: array of string names for all possible parents
306 * @parent_data: array of parent data for all possible parents (when some
307 * parents are external to the clk controller)
308 * @parent_hws: array of pointers to all possible parents (when all parents
309 * are internal to the clk controller)
310 * @num_parents: number of possible parents
311 * @flags: framework-level hints and quirks
312 */
313 struct clk_init_data {
314 const char *name;
315 const struct clk_ops *ops;
316 /* Only one of the following three should be assigned */
317 const char * const *parent_names;
318 const struct clk_parent_data *parent_data;
319 const struct clk_hw **parent_hws;
320 u8 num_parents;
321 unsigned long flags;
322 };
323
324 /**
325 * struct clk_hw - handle for traversing from a struct clk to its corresponding
326 * hardware-specific structure. struct clk_hw should be declared within struct
327 * clk_foo and then referenced by the struct clk instance that uses struct
328 * clk_foo's clk_ops
329 *
330 * @core: pointer to the struct clk_core instance that points back to this
331 * struct clk_hw instance
332 *
333 * @clk: pointer to the per-user struct clk instance that can be used to call
334 * into the clk API
335 *
336 * @init: pointer to struct clk_init_data that contains the init data shared
337 * with the common clock framework. This pointer will be set to NULL once
338 * a clk_register() variant is called on this clk_hw pointer.
339 */
340 struct clk_hw {
341 struct clk_core *core;
342 struct clk *clk;
343 const struct clk_init_data *init;
344 };
345
346 /*
347 * DOC: Basic clock implementations common to many platforms
348 *
349 * Each basic clock hardware type is comprised of a structure describing the
350 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
351 * unique flags for that hardware type, a registration function and an
352 * alternative macro for static initialization
353 */
354
355 /**
356 * struct clk_fixed_rate - fixed-rate clock
357 * @hw: handle between common and hardware-specific interfaces
358 * @fixed_rate: constant frequency of clock
359 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
360 * @flags: hardware specific flags
361 *
362 * Flags:
363 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
364 * instead of what's set in @fixed_accuracy.
365 */
366 struct clk_fixed_rate {
367 struct clk_hw hw;
368 unsigned long fixed_rate;
369 unsigned long fixed_accuracy;
370 unsigned long flags;
371 };
372
373 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
374
375 extern const struct clk_ops clk_fixed_rate_ops;
376 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
377 struct device_node *np, const char *name,
378 const char *parent_name, const struct clk_hw *parent_hw,
379 const struct clk_parent_data *parent_data, unsigned long flags,
380 unsigned long fixed_rate, unsigned long fixed_accuracy,
381 unsigned long clk_fixed_flags, bool devm);
382 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
383 const char *parent_name, unsigned long flags,
384 unsigned long fixed_rate);
385 /**
386 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
387 * framework
388 * @dev: device that is registering this clock
389 * @name: name of this clock
390 * @parent_name: name of clock's parent
391 * @flags: framework-specific flags
392 * @fixed_rate: non-adjustable clock rate
393 */
394 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
395 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
396 NULL, (flags), (fixed_rate), 0, 0, false)
397
398 /**
399 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
400 * framework
401 * @dev: device that is registering this clock
402 * @name: name of this clock
403 * @parent_name: name of clock's parent
404 * @flags: framework-specific flags
405 * @fixed_rate: non-adjustable clock rate
406 */
407 #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
408 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
409 NULL, (flags), (fixed_rate), 0, 0, true)
410 /**
411 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
412 * the clock framework
413 * @dev: device that is registering this clock
414 * @name: name of this clock
415 * @parent_hw: pointer to parent clk
416 * @flags: framework-specific flags
417 * @fixed_rate: non-adjustable clock rate
418 */
419 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
420 fixed_rate) \
421 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
422 NULL, (flags), (fixed_rate), 0, 0, false)
423 /**
424 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
425 * the clock framework
426 * @dev: device that is registering this clock
427 * @name: name of this clock
428 * @parent_data: parent clk data
429 * @flags: framework-specific flags
430 * @fixed_rate: non-adjustable clock rate
431 */
432 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \
433 fixed_rate) \
434 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
435 (parent_data), (flags), (fixed_rate), 0, \
436 0, false)
437 /**
438 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
439 * the clock framework
440 * @dev: device that is registering this clock
441 * @name: name of this clock
442 * @parent_name: name of clock's parent
443 * @flags: framework-specific flags
444 * @fixed_rate: non-adjustable clock rate
445 * @fixed_accuracy: non-adjustable clock accuracy
446 */
447 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
448 flags, fixed_rate, \
449 fixed_accuracy) \
450 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
451 NULL, NULL, (flags), (fixed_rate), \
452 (fixed_accuracy), 0, false)
453 /**
454 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
455 * clock with the clock framework
456 * @dev: device that is registering this clock
457 * @name: name of this clock
458 * @parent_hw: pointer to parent clk
459 * @flags: framework-specific flags
460 * @fixed_rate: non-adjustable clock rate
461 * @fixed_accuracy: non-adjustable clock accuracy
462 */
463 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
464 parent_hw, flags, fixed_rate, fixed_accuracy) \
465 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
466 NULL, (flags), (fixed_rate), \
467 (fixed_accuracy), 0, false)
468 /**
469 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
470 * clock with the clock framework
471 * @dev: device that is registering this clock
472 * @name: name of this clock
473 * @parent_data: name of clock's parent
474 * @flags: framework-specific flags
475 * @fixed_rate: non-adjustable clock rate
476 * @fixed_accuracy: non-adjustable clock accuracy
477 */
478 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
479 parent_data, flags, fixed_rate, fixed_accuracy) \
480 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
481 (parent_data), NULL, (flags), \
482 (fixed_rate), (fixed_accuracy), 0, false)
483 /**
484 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
485 * the clock framework
486 * @dev: device that is registering this clock
487 * @name: name of this clock
488 * @parent_data: name of clock's parent
489 * @flags: framework-specific flags
490 * @fixed_rate: non-adjustable clock rate
491 */
492 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
493 flags, fixed_rate) \
494 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
495 (parent_data), (flags), (fixed_rate), 0, \
496 CLK_FIXED_RATE_PARENT_ACCURACY, false)
497
498 void clk_unregister_fixed_rate(struct clk *clk);
499 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
500
501 void of_fixed_clk_setup(struct device_node *np);
502
503 /**
504 * struct clk_gate - gating clock
505 *
506 * @hw: handle between common and hardware-specific interfaces
507 * @reg: register controlling gate
508 * @bit_idx: single bit controlling gate
509 * @flags: hardware-specific flags
510 * @lock: register lock
511 *
512 * Clock which can gate its output. Implements .enable & .disable
513 *
514 * Flags:
515 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
516 * enable the clock. Setting this flag does the opposite: setting the bit
517 * disable the clock and clearing it enables the clock
518 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
519 * of this register, and mask of gate bits are in higher 16-bit of this
520 * register. While setting the gate bits, higher 16-bit should also be
521 * updated to indicate changing gate bits.
522 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
523 * the gate register. Setting this flag makes the register accesses big
524 * endian.
525 */
526 struct clk_gate {
527 struct clk_hw hw;
528 void __iomem *reg;
529 u8 bit_idx;
530 u8 flags;
531 spinlock_t *lock;
532 };
533
534 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
535
536 #define CLK_GATE_SET_TO_DISABLE BIT(0)
537 #define CLK_GATE_HIWORD_MASK BIT(1)
538 #define CLK_GATE_BIG_ENDIAN BIT(2)
539
540 extern const struct clk_ops clk_gate_ops;
541 struct clk_hw *__clk_hw_register_gate(struct device *dev,
542 struct device_node *np, const char *name,
543 const char *parent_name, const struct clk_hw *parent_hw,
544 const struct clk_parent_data *parent_data,
545 unsigned long flags,
546 void __iomem *reg, u8 bit_idx,
547 u8 clk_gate_flags, spinlock_t *lock);
548 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
549 struct device_node *np, const char *name,
550 const char *parent_name, const struct clk_hw *parent_hw,
551 const struct clk_parent_data *parent_data,
552 unsigned long flags,
553 void __iomem *reg, u8 bit_idx,
554 u8 clk_gate_flags, spinlock_t *lock);
555 struct clk *clk_register_gate(struct device *dev, const char *name,
556 const char *parent_name, unsigned long flags,
557 void __iomem *reg, u8 bit_idx,
558 u8 clk_gate_flags, spinlock_t *lock);
559 /**
560 * clk_hw_register_gate - register a gate clock with the clock framework
561 * @dev: device that is registering this clock
562 * @name: name of this clock
563 * @parent_name: name of this clock's parent
564 * @flags: framework-specific flags for this clock
565 * @reg: register address to control gating of this clock
566 * @bit_idx: which bit in the register controls gating of this clock
567 * @clk_gate_flags: gate-specific flags for this clock
568 * @lock: shared register lock for this clock
569 */
570 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
571 clk_gate_flags, lock) \
572 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
573 NULL, (flags), (reg), (bit_idx), \
574 (clk_gate_flags), (lock))
575 /**
576 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
577 * framework
578 * @dev: device that is registering this clock
579 * @name: name of this clock
580 * @parent_hw: pointer to parent clk
581 * @flags: framework-specific flags for this clock
582 * @reg: register address to control gating of this clock
583 * @bit_idx: which bit in the register controls gating of this clock
584 * @clk_gate_flags: gate-specific flags for this clock
585 * @lock: shared register lock for this clock
586 */
587 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
588 bit_idx, clk_gate_flags, lock) \
589 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
590 NULL, (flags), (reg), (bit_idx), \
591 (clk_gate_flags), (lock))
592 /**
593 * clk_hw_register_gate_parent_data - register a gate clock with the clock
594 * framework
595 * @dev: device that is registering this clock
596 * @name: name of this clock
597 * @parent_data: parent clk data
598 * @flags: framework-specific flags for this clock
599 * @reg: register address to control gating of this clock
600 * @bit_idx: which bit in the register controls gating of this clock
601 * @clk_gate_flags: gate-specific flags for this clock
602 * @lock: shared register lock for this clock
603 */
604 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
605 bit_idx, clk_gate_flags, lock) \
606 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
607 (flags), (reg), (bit_idx), \
608 (clk_gate_flags), (lock))
609 /**
610 * devm_clk_hw_register_gate - register a gate clock with the clock framework
611 * @dev: device that is registering this clock
612 * @name: name of this clock
613 * @parent_name: name of this clock's parent
614 * @flags: framework-specific flags for this clock
615 * @reg: register address to control gating of this clock
616 * @bit_idx: which bit in the register controls gating of this clock
617 * @clk_gate_flags: gate-specific flags for this clock
618 * @lock: shared register lock for this clock
619 */
620 #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
621 clk_gate_flags, lock) \
622 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
623 NULL, (flags), (reg), (bit_idx), \
624 (clk_gate_flags), (lock))
625 /**
626 * devm_clk_hw_register_gate_parent_data - register a gate clock with the
627 * clock framework
628 * @dev: device that is registering this clock
629 * @name: name of this clock
630 * @parent_data: parent clk data
631 * @flags: framework-specific flags for this clock
632 * @reg: register address to control gating of this clock
633 * @bit_idx: which bit in the register controls gating of this clock
634 * @clk_gate_flags: gate-specific flags for this clock
635 * @lock: shared register lock for this clock
636 */
637 #define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \
638 reg, bit_idx, clk_gate_flags, \
639 lock) \
640 __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \
641 (parent_data), (flags), (reg), (bit_idx), \
642 (clk_gate_flags), (lock))
643
644 void clk_unregister_gate(struct clk *clk);
645 void clk_hw_unregister_gate(struct clk_hw *hw);
646 int clk_gate_is_enabled(struct clk_hw *hw);
647
648 struct clk_div_table {
649 unsigned int val;
650 unsigned int div;
651 };
652
653 /**
654 * struct clk_divider - adjustable divider clock
655 *
656 * @hw: handle between common and hardware-specific interfaces
657 * @reg: register containing the divider
658 * @shift: shift to the divider bit field
659 * @width: width of the divider bit field
660 * @table: array of value/divider pairs, last entry should have div = 0
661 * @lock: register lock
662 *
663 * Clock with an adjustable divider affecting its output frequency. Implements
664 * .recalc_rate, .set_rate and .round_rate
665 *
666 * @flags:
667 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
668 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
669 * the raw value read from the register, with the value of zero considered
670 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
671 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
672 * the hardware register
673 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
674 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
675 * Some hardware implementations gracefully handle this case and allow a
676 * zero divisor by not modifying their input clock
677 * (divide by one / bypass).
678 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
679 * of this register, and mask of divider bits are in higher 16-bit of this
680 * register. While setting the divider bits, higher 16-bit should also be
681 * updated to indicate changing divider bits.
682 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
683 * to the closest integer instead of the up one.
684 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
685 * not be changed by the clock framework.
686 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
687 * except when the value read from the register is zero, the divisor is
688 * 2^width of the field.
689 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
690 * for the divider register. Setting this flag makes the register accesses
691 * big endian.
692 */
693 struct clk_divider {
694 struct clk_hw hw;
695 void __iomem *reg;
696 u8 shift;
697 u8 width;
698 u8 flags;
699 const struct clk_div_table *table;
700 spinlock_t *lock;
701 };
702
703 #define clk_div_mask(width) ((1 << (width)) - 1)
704 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
705
706 #define CLK_DIVIDER_ONE_BASED BIT(0)
707 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
708 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
709 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
710 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
711 #define CLK_DIVIDER_READ_ONLY BIT(5)
712 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
713 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
714
715 extern const struct clk_ops clk_divider_ops;
716 extern const struct clk_ops clk_divider_ro_ops;
717
718 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
719 unsigned int val, const struct clk_div_table *table,
720 unsigned long flags, unsigned long width);
721 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
722 unsigned long rate, unsigned long *prate,
723 const struct clk_div_table *table,
724 u8 width, unsigned long flags);
725 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
726 unsigned long rate, unsigned long *prate,
727 const struct clk_div_table *table, u8 width,
728 unsigned long flags, unsigned int val);
729 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
730 const struct clk_div_table *table, u8 width,
731 unsigned long flags);
732 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
733 const struct clk_div_table *table, u8 width,
734 unsigned long flags, unsigned int val);
735 int divider_get_val(unsigned long rate, unsigned long parent_rate,
736 const struct clk_div_table *table, u8 width,
737 unsigned long flags);
738
739 struct clk_hw *__clk_hw_register_divider(struct device *dev,
740 struct device_node *np, const char *name,
741 const char *parent_name, const struct clk_hw *parent_hw,
742 const struct clk_parent_data *parent_data, unsigned long flags,
743 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
744 const struct clk_div_table *table, spinlock_t *lock);
745 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
746 struct device_node *np, const char *name,
747 const char *parent_name, const struct clk_hw *parent_hw,
748 const struct clk_parent_data *parent_data, unsigned long flags,
749 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
750 const struct clk_div_table *table, spinlock_t *lock);
751 struct clk *clk_register_divider_table(struct device *dev, const char *name,
752 const char *parent_name, unsigned long flags,
753 void __iomem *reg, u8 shift, u8 width,
754 u8 clk_divider_flags, const struct clk_div_table *table,
755 spinlock_t *lock);
756 /**
757 * clk_register_divider - register a divider clock with the clock framework
758 * @dev: device registering this clock
759 * @name: name of this clock
760 * @parent_name: name of clock's parent
761 * @flags: framework-specific flags
762 * @reg: register address to adjust divider
763 * @shift: number of bits to shift the bitfield
764 * @width: width of the bitfield
765 * @clk_divider_flags: divider-specific flags for this clock
766 * @lock: shared register lock for this clock
767 */
768 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
769 clk_divider_flags, lock) \
770 clk_register_divider_table((dev), (name), (parent_name), (flags), \
771 (reg), (shift), (width), \
772 (clk_divider_flags), NULL, (lock))
773 /**
774 * clk_hw_register_divider - register a divider clock with the clock framework
775 * @dev: device registering this clock
776 * @name: name of this clock
777 * @parent_name: name of clock's parent
778 * @flags: framework-specific flags
779 * @reg: register address to adjust divider
780 * @shift: number of bits to shift the bitfield
781 * @width: width of the bitfield
782 * @clk_divider_flags: divider-specific flags for this clock
783 * @lock: shared register lock for this clock
784 */
785 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
786 width, clk_divider_flags, lock) \
787 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
788 NULL, (flags), (reg), (shift), (width), \
789 (clk_divider_flags), NULL, (lock))
790 /**
791 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
792 * framework
793 * @dev: device registering this clock
794 * @name: name of this clock
795 * @parent_hw: pointer to parent clk
796 * @flags: framework-specific flags
797 * @reg: register address to adjust divider
798 * @shift: number of bits to shift the bitfield
799 * @width: width of the bitfield
800 * @clk_divider_flags: divider-specific flags for this clock
801 * @lock: shared register lock for this clock
802 */
803 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
804 shift, width, clk_divider_flags, \
805 lock) \
806 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
807 NULL, (flags), (reg), (shift), (width), \
808 (clk_divider_flags), NULL, (lock))
809 /**
810 * clk_hw_register_divider_parent_data - register a divider clock with the clock
811 * framework
812 * @dev: device registering this clock
813 * @name: name of this clock
814 * @parent_data: parent clk data
815 * @flags: framework-specific flags
816 * @reg: register address to adjust divider
817 * @shift: number of bits to shift the bitfield
818 * @width: width of the bitfield
819 * @clk_divider_flags: divider-specific flags for this clock
820 * @lock: shared register lock for this clock
821 */
822 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
823 reg, shift, width, \
824 clk_divider_flags, lock) \
825 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
826 (parent_data), (flags), (reg), (shift), \
827 (width), (clk_divider_flags), NULL, (lock))
828 /**
829 * clk_hw_register_divider_table - register a table based divider clock with
830 * the clock framework
831 * @dev: device registering this clock
832 * @name: name of this clock
833 * @parent_name: name of clock's parent
834 * @flags: framework-specific flags
835 * @reg: register address to adjust divider
836 * @shift: number of bits to shift the bitfield
837 * @width: width of the bitfield
838 * @clk_divider_flags: divider-specific flags for this clock
839 * @table: array of divider/value pairs ending with a div set to 0
840 * @lock: shared register lock for this clock
841 */
842 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
843 shift, width, clk_divider_flags, table, \
844 lock) \
845 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
846 NULL, (flags), (reg), (shift), (width), \
847 (clk_divider_flags), (table), (lock))
848 /**
849 * clk_hw_register_divider_table_parent_hw - register a table based divider
850 * clock with the clock framework
851 * @dev: device registering this clock
852 * @name: name of this clock
853 * @parent_hw: pointer to parent clk
854 * @flags: framework-specific flags
855 * @reg: register address to adjust divider
856 * @shift: number of bits to shift the bitfield
857 * @width: width of the bitfield
858 * @clk_divider_flags: divider-specific flags for this clock
859 * @table: array of divider/value pairs ending with a div set to 0
860 * @lock: shared register lock for this clock
861 */
862 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
863 reg, shift, width, \
864 clk_divider_flags, table, \
865 lock) \
866 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
867 NULL, (flags), (reg), (shift), (width), \
868 (clk_divider_flags), (table), (lock))
869 /**
870 * clk_hw_register_divider_table_parent_data - register a table based divider
871 * clock with the clock framework
872 * @dev: device registering this clock
873 * @name: name of this clock
874 * @parent_data: parent clk data
875 * @flags: framework-specific flags
876 * @reg: register address to adjust divider
877 * @shift: number of bits to shift the bitfield
878 * @width: width of the bitfield
879 * @clk_divider_flags: divider-specific flags for this clock
880 * @table: array of divider/value pairs ending with a div set to 0
881 * @lock: shared register lock for this clock
882 */
883 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
884 flags, reg, shift, width, \
885 clk_divider_flags, table, \
886 lock) \
887 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
888 (parent_data), (flags), (reg), (shift), \
889 (width), (clk_divider_flags), (table), \
890 (lock))
891 /**
892 * devm_clk_hw_register_divider - register a divider clock with the clock framework
893 * @dev: device registering this clock
894 * @name: name of this clock
895 * @parent_name: name of clock's parent
896 * @flags: framework-specific flags
897 * @reg: register address to adjust divider
898 * @shift: number of bits to shift the bitfield
899 * @width: width of the bitfield
900 * @clk_divider_flags: divider-specific flags for this clock
901 * @lock: shared register lock for this clock
902 */
903 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
904 width, clk_divider_flags, lock) \
905 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
906 NULL, (flags), (reg), (shift), (width), \
907 (clk_divider_flags), NULL, (lock))
908 /**
909 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
910 * @dev: device registering this clock
911 * @name: name of this clock
912 * @parent_hw: pointer to parent clk
913 * @flags: framework-specific flags
914 * @reg: register address to adjust divider
915 * @shift: number of bits to shift the bitfield
916 * @width: width of the bitfield
917 * @clk_divider_flags: divider-specific flags for this clock
918 * @lock: shared register lock for this clock
919 */
920 #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \
921 reg, shift, width, \
922 clk_divider_flags, lock) \
923 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
924 (parent_hw), NULL, (flags), (reg), \
925 (shift), (width), (clk_divider_flags), \
926 NULL, (lock))
927 /**
928 * devm_clk_hw_register_divider_table - register a table based divider clock
929 * with the clock framework (devres variant)
930 * @dev: device registering this clock
931 * @name: name of this clock
932 * @parent_name: name of clock's parent
933 * @flags: framework-specific flags
934 * @reg: register address to adjust divider
935 * @shift: number of bits to shift the bitfield
936 * @width: width of the bitfield
937 * @clk_divider_flags: divider-specific flags for this clock
938 * @table: array of divider/value pairs ending with a div set to 0
939 * @lock: shared register lock for this clock
940 */
941 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
942 reg, shift, width, \
943 clk_divider_flags, table, lock) \
944 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
945 NULL, NULL, (flags), (reg), (shift), \
946 (width), (clk_divider_flags), (table), \
947 (lock))
948
949 void clk_unregister_divider(struct clk *clk);
950 void clk_hw_unregister_divider(struct clk_hw *hw);
951
952 /**
953 * struct clk_mux - multiplexer clock
954 *
955 * @hw: handle between common and hardware-specific interfaces
956 * @reg: register controlling multiplexer
957 * @table: array of register values corresponding to the parent index
958 * @shift: shift to multiplexer bit field
959 * @mask: mask of mutliplexer bit field
960 * @flags: hardware-specific flags
961 * @lock: register lock
962 *
963 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
964 * and .recalc_rate
965 *
966 * Flags:
967 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
968 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
969 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
970 * register, and mask of mux bits are in higher 16-bit of this register.
971 * While setting the mux bits, higher 16-bit should also be updated to
972 * indicate changing mux bits.
973 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
974 * .get_parent clk_op.
975 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
976 * frequency.
977 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
978 * the mux register. Setting this flag makes the register accesses big
979 * endian.
980 */
981 struct clk_mux {
982 struct clk_hw hw;
983 void __iomem *reg;
984 const u32 *table;
985 u32 mask;
986 u8 shift;
987 u8 flags;
988 spinlock_t *lock;
989 };
990
991 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
992
993 #define CLK_MUX_INDEX_ONE BIT(0)
994 #define CLK_MUX_INDEX_BIT BIT(1)
995 #define CLK_MUX_HIWORD_MASK BIT(2)
996 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
997 #define CLK_MUX_ROUND_CLOSEST BIT(4)
998 #define CLK_MUX_BIG_ENDIAN BIT(5)
999
1000 extern const struct clk_ops clk_mux_ops;
1001 extern const struct clk_ops clk_mux_ro_ops;
1002
1003 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
1004 const char *name, u8 num_parents,
1005 const char * const *parent_names,
1006 const struct clk_hw **parent_hws,
1007 const struct clk_parent_data *parent_data,
1008 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1009 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1010 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
1011 const char *name, u8 num_parents,
1012 const char * const *parent_names,
1013 const struct clk_hw **parent_hws,
1014 const struct clk_parent_data *parent_data,
1015 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1016 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1017 struct clk *clk_register_mux_table(struct device *dev, const char *name,
1018 const char * const *parent_names, u8 num_parents,
1019 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1020 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1021
1022 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1023 shift, width, clk_mux_flags, lock) \
1024 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
1025 (flags), (reg), (shift), BIT((width)) - 1, \
1026 (clk_mux_flags), NULL, (lock))
1027 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
1028 flags, reg, shift, mask, clk_mux_flags, \
1029 table, lock) \
1030 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1031 (parent_names), NULL, NULL, (flags), (reg), \
1032 (shift), (mask), (clk_mux_flags), (table), \
1033 (lock))
1034 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
1035 num_parents, flags, reg, shift, mask, \
1036 clk_mux_flags, table, lock) \
1037 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1038 NULL, NULL, (parent_data), (flags), (reg), \
1039 (shift), (mask), (clk_mux_flags), (table), \
1040 (lock))
1041 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1042 shift, width, clk_mux_flags, lock) \
1043 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1044 (parent_names), NULL, NULL, (flags), (reg), \
1045 (shift), BIT((width)) - 1, (clk_mux_flags), \
1046 NULL, (lock))
1047 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
1048 reg, shift, width, clk_mux_flags, lock) \
1049 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1050 (parent_hws), NULL, (flags), (reg), (shift), \
1051 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1052 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
1053 flags, reg, shift, width, \
1054 clk_mux_flags, lock) \
1055 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1056 (parent_data), (flags), (reg), (shift), \
1057 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1058 #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1059 num_parents, flags, reg, shift, \
1060 width, clk_mux_flags, table, \
1061 lock) \
1062 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1063 (parent_data), (flags), (reg), (shift), \
1064 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1065 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1066 shift, width, clk_mux_flags, lock) \
1067 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1068 (parent_names), NULL, NULL, (flags), (reg), \
1069 (shift), BIT((width)) - 1, (clk_mux_flags), \
1070 NULL, (lock))
1071 #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \
1072 num_parents, flags, reg, shift, \
1073 width, clk_mux_flags, lock) \
1074 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1075 (parent_hws), NULL, (flags), (reg), \
1076 (shift), BIT((width)) - 1, \
1077 (clk_mux_flags), NULL, (lock))
1078 #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1079 num_parents, flags, reg, shift, \
1080 width, clk_mux_flags, table, \
1081 lock) \
1082 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1083 NULL, (parent_data), (flags), (reg), (shift), \
1084 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1085
1086 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
1087 unsigned int val);
1088 unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);
1089
1090 void clk_unregister_mux(struct clk *clk);
1091 void clk_hw_unregister_mux(struct clk_hw *hw);
1092
1093 void of_fixed_factor_clk_setup(struct device_node *node);
1094
1095 /**
1096 * struct clk_fixed_factor - fixed multiplier and divider clock
1097 *
1098 * @hw: handle between common and hardware-specific interfaces
1099 * @mult: multiplier
1100 * @div: divider
1101 *
1102 * Clock with a fixed multiplier and divider. The output frequency is the
1103 * parent clock rate divided by div and multiplied by mult.
1104 * Implements .recalc_rate, .set_rate and .round_rate
1105 */
1106
1107 struct clk_fixed_factor {
1108 struct clk_hw hw;
1109 unsigned int mult;
1110 unsigned int div;
1111 };
1112
1113 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
1114
1115 extern const struct clk_ops clk_fixed_factor_ops;
1116 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1117 const char *parent_name, unsigned long flags,
1118 unsigned int mult, unsigned int div);
1119 void clk_unregister_fixed_factor(struct clk *clk);
1120 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1121 const char *name, const char *parent_name, unsigned long flags,
1122 unsigned int mult, unsigned int div);
1123 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1124 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1125 const char *name, const char *parent_name, unsigned long flags,
1126 unsigned int mult, unsigned int div);
1127 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1128 const char *name, unsigned int index, unsigned long flags,
1129 unsigned int mult, unsigned int div);
1130
1131 struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1132 const char *name, const struct clk_hw *parent_hw,
1133 unsigned long flags, unsigned int mult, unsigned int div);
1134
1135 struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1136 const char *name, const struct clk_hw *parent_hw,
1137 unsigned long flags, unsigned int mult, unsigned int div);
1138 /**
1139 * struct clk_fractional_divider - adjustable fractional divider clock
1140 *
1141 * @hw: handle between common and hardware-specific interfaces
1142 * @reg: register containing the divider
1143 * @mshift: shift to the numerator bit field
1144 * @mwidth: width of the numerator bit field
1145 * @nshift: shift to the denominator bit field
1146 * @nwidth: width of the denominator bit field
1147 * @approximation: clk driver's callback for calculating the divider clock
1148 * @lock: register lock
1149 *
1150 * Clock with adjustable fractional divider affecting its output frequency.
1151 *
1152 * @flags:
1153 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1154 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
1155 * is set then the numerator and denominator are both the value read
1156 * plus one.
1157 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1158 * used for the divider register. Setting this flag makes the register
1159 * accesses big endian.
1160 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1161 * be saturated and the caller will get quite far from the good enough
1162 * approximation. Instead the caller may require, by setting this flag,
1163 * to shift left by a few bits in case, when the asked one is quite small
1164 * to satisfy the desired range of denominator. It assumes that on the
1165 * caller's side the power-of-two capable prescaler exists.
1166 */
1167 struct clk_fractional_divider {
1168 struct clk_hw hw;
1169 void __iomem *reg;
1170 u8 mshift;
1171 u8 mwidth;
1172 u8 nshift;
1173 u8 nwidth;
1174 u8 flags;
1175 void (*approximation)(struct clk_hw *hw,
1176 unsigned long rate, unsigned long *parent_rate,
1177 unsigned long *m, unsigned long *n);
1178 spinlock_t *lock;
1179 };
1180
1181 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1182
1183 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1184 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1185 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1186
1187 struct clk *clk_register_fractional_divider(struct device *dev,
1188 const char *name, const char *parent_name, unsigned long flags,
1189 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1190 u8 clk_divider_flags, spinlock_t *lock);
1191 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1192 const char *name, const char *parent_name, unsigned long flags,
1193 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1194 u8 clk_divider_flags, spinlock_t *lock);
1195 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1196
1197 /**
1198 * struct clk_multiplier - adjustable multiplier clock
1199 *
1200 * @hw: handle between common and hardware-specific interfaces
1201 * @reg: register containing the multiplier
1202 * @shift: shift to the multiplier bit field
1203 * @width: width of the multiplier bit field
1204 * @lock: register lock
1205 *
1206 * Clock with an adjustable multiplier affecting its output frequency.
1207 * Implements .recalc_rate, .set_rate and .round_rate
1208 *
1209 * @flags:
1210 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1211 * from the register, with 0 being a valid value effectively
1212 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1213 * set, then a null multiplier will be considered as a bypass,
1214 * leaving the parent rate unmodified.
1215 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1216 * rounded to the closest integer instead of the down one.
1217 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1218 * used for the multiplier register. Setting this flag makes the register
1219 * accesses big endian.
1220 */
1221 struct clk_multiplier {
1222 struct clk_hw hw;
1223 void __iomem *reg;
1224 u8 shift;
1225 u8 width;
1226 u8 flags;
1227 spinlock_t *lock;
1228 };
1229
1230 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1231
1232 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1233 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1234 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1235
1236 extern const struct clk_ops clk_multiplier_ops;
1237
1238 /***
1239 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1240 *
1241 * @hw: handle between common and hardware-specific interfaces
1242 * @mux_hw: handle between composite and hardware-specific mux clock
1243 * @rate_hw: handle between composite and hardware-specific rate clock
1244 * @gate_hw: handle between composite and hardware-specific gate clock
1245 * @mux_ops: clock ops for mux
1246 * @rate_ops: clock ops for rate
1247 * @gate_ops: clock ops for gate
1248 */
1249 struct clk_composite {
1250 struct clk_hw hw;
1251 struct clk_ops ops;
1252
1253 struct clk_hw *mux_hw;
1254 struct clk_hw *rate_hw;
1255 struct clk_hw *gate_hw;
1256
1257 const struct clk_ops *mux_ops;
1258 const struct clk_ops *rate_ops;
1259 const struct clk_ops *gate_ops;
1260 };
1261
1262 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1263
1264 struct clk *clk_register_composite(struct device *dev, const char *name,
1265 const char * const *parent_names, int num_parents,
1266 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1267 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1268 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1269 unsigned long flags);
1270 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1271 const struct clk_parent_data *parent_data, int num_parents,
1272 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1273 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1274 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1275 unsigned long flags);
1276 void clk_unregister_composite(struct clk *clk);
1277 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1278 const char * const *parent_names, int num_parents,
1279 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1280 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1281 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1282 unsigned long flags);
1283 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1284 const char *name,
1285 const struct clk_parent_data *parent_data, int num_parents,
1286 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1287 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1288 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1289 unsigned long flags);
1290 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1291 const char *name, const struct clk_parent_data *parent_data,
1292 int num_parents,
1293 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1294 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1295 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1296 unsigned long flags);
1297 void clk_hw_unregister_composite(struct clk_hw *hw);
1298
1299 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1300 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1301
1302 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1303 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1304 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1305
1306 void clk_unregister(struct clk *clk);
1307
1308 void clk_hw_unregister(struct clk_hw *hw);
1309 void clk_sync_state(struct device *dev);
1310
1311 /* helper functions */
1312 const char *__clk_get_name(const struct clk *clk);
1313 const char *clk_hw_get_name(const struct clk_hw *hw);
1314 #ifdef CONFIG_COMMON_CLK
1315 struct clk_hw *__clk_get_hw(struct clk *clk);
1316 #else
__clk_get_hw(struct clk * clk)1317 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1318 {
1319 return (struct clk_hw *)clk;
1320 }
1321 #endif
1322
1323 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1324 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1325 const char *con_id);
1326
1327 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1328 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1329 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1330 unsigned int index);
1331 int clk_hw_get_parent_index(struct clk_hw *hw);
1332 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1333 unsigned int __clk_get_enable_count(struct clk *clk);
1334 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1335 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1336 #define clk_hw_can_set_rate_parent(hw) \
1337 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1338
1339 bool clk_hw_is_prepared(const struct clk_hw *hw);
1340 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1341 bool clk_hw_is_enabled(const struct clk_hw *hw);
1342 bool __clk_is_enabled(struct clk *clk);
1343 struct clk *__clk_lookup(const char *name);
1344 int __clk_mux_determine_rate(struct clk_hw *hw,
1345 struct clk_rate_request *req);
1346 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1347 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1348 struct clk_rate_request *req);
1349 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1350 struct clk_rate_request *req,
1351 unsigned long flags);
1352 int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,
1353 struct clk_rate_request *req);
1354 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1355 void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
1356 unsigned long *max_rate);
1357 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1358 unsigned long max_rate);
1359
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1360 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1361 {
1362 dst->clk = src->clk;
1363 dst->core = src->core;
1364 }
1365
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1366 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1367 unsigned long *prate,
1368 const struct clk_div_table *table,
1369 u8 width, unsigned long flags)
1370 {
1371 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1372 rate, prate, table, width, flags);
1373 }
1374
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1375 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1376 unsigned long *prate,
1377 const struct clk_div_table *table,
1378 u8 width, unsigned long flags,
1379 unsigned int val)
1380 {
1381 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1382 rate, prate, table, width, flags,
1383 val);
1384 }
1385
1386 /*
1387 * FIXME clock api without lock protection
1388 */
1389 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1390
1391 struct clk_onecell_data {
1392 struct clk **clks;
1393 unsigned int clk_num;
1394 };
1395
1396 struct clk_hw_onecell_data {
1397 unsigned int num;
1398 struct clk_hw *hws[] __counted_by(num);
1399 };
1400
1401 #define CLK_OF_DECLARE(name, compat, fn) \
1402 static void __init __##name##_of_clk_init_declare(struct device_node *np) \
1403 { \
1404 fn(np); \
1405 fwnode_dev_initialized(of_fwnode_handle(np), true); \
1406 } \
1407 OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare)
1408
1409 /*
1410 * Use this macro when you have a driver that requires two initialization
1411 * routines, one at of_clk_init(), and one at platform device probe
1412 */
1413 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1414 static void __init name##_of_clk_init_driver(struct device_node *np) \
1415 { \
1416 of_node_clear_flag(np, OF_POPULATED); \
1417 fn(np); \
1418 } \
1419 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1420
1421 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1422 (&(struct clk_init_data) { \
1423 .flags = _flags, \
1424 .name = _name, \
1425 .parent_names = (const char *[]) { _parent }, \
1426 .num_parents = 1, \
1427 .ops = _ops, \
1428 })
1429
1430 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1431 (&(struct clk_init_data) { \
1432 .flags = _flags, \
1433 .name = _name, \
1434 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1435 .num_parents = 1, \
1436 .ops = _ops, \
1437 })
1438
1439 /*
1440 * This macro is intended for drivers to be able to share the otherwise
1441 * individual struct clk_hw[] compound literals created by the compiler
1442 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1443 */
1444 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1445 (&(struct clk_init_data) { \
1446 .flags = _flags, \
1447 .name = _name, \
1448 .parent_hws = _parent, \
1449 .num_parents = 1, \
1450 .ops = _ops, \
1451 })
1452
1453 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1454 (&(struct clk_init_data) { \
1455 .flags = _flags, \
1456 .name = _name, \
1457 .parent_data = (const struct clk_parent_data[]) { \
1458 { .fw_name = _parent }, \
1459 }, \
1460 .num_parents = 1, \
1461 .ops = _ops, \
1462 })
1463
1464 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1465 (&(struct clk_init_data) { \
1466 .flags = _flags, \
1467 .name = _name, \
1468 .parent_names = _parents, \
1469 .num_parents = ARRAY_SIZE(_parents), \
1470 .ops = _ops, \
1471 })
1472
1473 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1474 (&(struct clk_init_data) { \
1475 .flags = _flags, \
1476 .name = _name, \
1477 .parent_hws = _parents, \
1478 .num_parents = ARRAY_SIZE(_parents), \
1479 .ops = _ops, \
1480 })
1481
1482 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1483 (&(struct clk_init_data) { \
1484 .flags = _flags, \
1485 .name = _name, \
1486 .parent_data = _parents, \
1487 .num_parents = ARRAY_SIZE(_parents), \
1488 .ops = _ops, \
1489 })
1490
1491 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1492 (&(struct clk_init_data) { \
1493 .flags = _flags, \
1494 .name = _name, \
1495 .parent_names = NULL, \
1496 .num_parents = 0, \
1497 .ops = _ops, \
1498 })
1499
1500 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1501 _div, _mult, _flags) \
1502 struct clk_fixed_factor _struct = { \
1503 .div = _div, \
1504 .mult = _mult, \
1505 .hw.init = CLK_HW_INIT(_name, \
1506 _parent, \
1507 &clk_fixed_factor_ops, \
1508 _flags), \
1509 }
1510
1511 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1512 _div, _mult, _flags) \
1513 struct clk_fixed_factor _struct = { \
1514 .div = _div, \
1515 .mult = _mult, \
1516 .hw.init = CLK_HW_INIT_HW(_name, \
1517 _parent, \
1518 &clk_fixed_factor_ops, \
1519 _flags), \
1520 }
1521
1522 /*
1523 * This macro allows the driver to reuse the _parent array for multiple
1524 * fixed factor clk declarations.
1525 */
1526 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1527 _div, _mult, _flags) \
1528 struct clk_fixed_factor _struct = { \
1529 .div = _div, \
1530 .mult = _mult, \
1531 .hw.init = CLK_HW_INIT_HWS(_name, \
1532 _parent, \
1533 &clk_fixed_factor_ops, \
1534 _flags), \
1535 }
1536
1537 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1538 _div, _mult, _flags) \
1539 struct clk_fixed_factor _struct = { \
1540 .div = _div, \
1541 .mult = _mult, \
1542 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1543 _parent, \
1544 &clk_fixed_factor_ops, \
1545 _flags), \
1546 }
1547
1548 #ifdef CONFIG_OF
1549 int of_clk_add_provider(struct device_node *np,
1550 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1551 void *data),
1552 void *data);
1553 int of_clk_add_hw_provider(struct device_node *np,
1554 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1555 void *data),
1556 void *data);
1557 int devm_of_clk_add_hw_provider(struct device *dev,
1558 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1559 void *data),
1560 void *data);
1561 void of_clk_del_provider(struct device_node *np);
1562
1563 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1564 void *data);
1565 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1566 void *data);
1567 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1568 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1569 void *data);
1570 int of_clk_parent_fill(struct device_node *np, const char **parents,
1571 unsigned int size);
1572 int of_clk_detect_critical(struct device_node *np, int index,
1573 unsigned long *flags);
1574
1575 #else /* !CONFIG_OF */
1576
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1577 static inline int of_clk_add_provider(struct device_node *np,
1578 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1579 void *data),
1580 void *data)
1581 {
1582 return 0;
1583 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1584 static inline int of_clk_add_hw_provider(struct device_node *np,
1585 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1586 void *data),
1587 void *data)
1588 {
1589 return 0;
1590 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1591 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1592 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1593 void *data),
1594 void *data)
1595 {
1596 return 0;
1597 }
of_clk_del_provider(struct device_node * np)1598 static inline void of_clk_del_provider(struct device_node *np) {}
1599
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1600 static inline struct clk *of_clk_src_simple_get(
1601 struct of_phandle_args *clkspec, void *data)
1602 {
1603 return ERR_PTR(-ENOENT);
1604 }
1605 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1606 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1607 {
1608 return ERR_PTR(-ENOENT);
1609 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1610 static inline struct clk *of_clk_src_onecell_get(
1611 struct of_phandle_args *clkspec, void *data)
1612 {
1613 return ERR_PTR(-ENOENT);
1614 }
1615 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1616 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1617 {
1618 return ERR_PTR(-ENOENT);
1619 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1620 static inline int of_clk_parent_fill(struct device_node *np,
1621 const char **parents, unsigned int size)
1622 {
1623 return 0;
1624 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1625 static inline int of_clk_detect_critical(struct device_node *np, int index,
1626 unsigned long *flags)
1627 {
1628 return 0;
1629 }
1630 #endif /* CONFIG_OF */
1631
1632 void clk_gate_restore_context(struct clk_hw *hw);
1633
1634 #endif /* CLK_PROVIDER_H */
1635