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Searched refs:A5 (Results 1 – 19 of 19) sorted by relevance

/arch/s390/crypto/
Dchacha-s390.S465 #define A5 %v20 macro
504 VLR A5,K0
531 VAF A5,A5,B5
537 VX D5,D5,A5
569 VAF A5,A5,B5
575 VX D5,D5,A5
626 VAF A5,A5,B5
632 VX D5,D5,A5
664 VAF A5,A5,B5
670 VX D5,D5,A5
[all …]
/arch/m68k/fpsp040/
Dsetox.S128 | p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))
130 | made as "short" as possible: A1 (which is 1/2), A4 and A5
138 | [ S*(A1 + S*(A3 + S*A5)) ]
513 |-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))
515 |--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))]
520 fmoves #0x3AB60B70,%fp2 | ...fp2 IS A5
523 fmulx %fp1,%fp2 | ...fp2 IS S*A5
527 faddd EXPA3,%fp2 | ...fp2 IS A3+S*A5
530 fmulx %fp1,%fp2 | ...fp2 IS S*(A3+S*A5)
538 fadds #0x3F000000,%fp2 | ...fp2 IS A1+S*(A3+S*A5)
[all …]
Dslogn.S388 |--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS
389 |--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))]
395 fmuld LOGA5,%fp2 | ...V*A5
398 faddd LOGA3,%fp2 | ...A3+V*A5
401 fmulx %fp3,%fp2 | ...V*(A3+V*A5)
404 faddd LOGA1,%fp2 | ...A1+V*(A3+V*A5)
408 fmulx %fp3,%fp2 | ...V*(A1+V*(A3+V*A5)), FP3 RELEASED
411 faddx %fp2,%fp0 | ...U+V*(A1+V*(A3+V*A5)), FP2 RELEASED
Dssin.S257 faddd SINA5,%fp3 | ...A5+TA7
260 fmulx %fp1,%fp3 | ...T(A5+TA7)
263 faddd SINA3,%fp3 | ...A3+T(A5+TA7)
266 fmulx %fp3,%fp1 | ...T(A3+T(A5+TA7))
269 faddx SINA1,%fp1 | ...A1+T(A3+T(A5+TA7))
609 faddd SINA5,%fp1 | ...A5+S(A6+SA7)
614 fmulx %fp0,%fp1 | ...S(A5+S(A6+SA7))
618 faddd SINA4,%fp1 | ...A4+S(A5+S(A6+SA7))
682 faddd SINA5,%fp2 | ...A5+S(A6+SA7)
685 fmulx %fp0,%fp2 | ...S(A5+S(A6+SA7))
[all …]
Dbinstr.S35 | A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5
102 | A5. Add mul by 8 to mul by 2. D1 contains the digit formed.
Dstwotox.S62 | P = r + r*r*(A1+r*(A2+...+r*A5)).
Dbindec.S39 | A5. Set ICTR = 0;
269 | A5. Set ICTR = 0;
Ddecbin.S56 | A5. Form the final binary number by scaling the mantissa by
/arch/arm/mach-versatile/
DKconfig276 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
287 bool "Enable A5 and A9 only errata work-arounds"
294 based on Cortex-A5 and Cortex-A9 processors. In order to
/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi54 mac-address = [ 02 A1 A2 A3 A4 A5 ];
/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca5s.dts6 * Cortex-A5 MPCore (V2P-CA5s)
/arch/arm64/boot/dts/ti/
Dk3-am65-iot2050-common.dtsi412 "IO1", "IO2", "", "IO3", "IO17-direction", "A5",
454 "A5-pull", "", "",
Dk3-j7200-som-p0.dtsi96 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
Dk3-am62-verdin.dtsi749 AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */
/arch/m68k/ifpsp060/src/
Dfplsp.S5102 fadd.d SINA5(%pc),%fp3 # A5+TA7
5105 fmul.x %fp1,%fp3 # T(A5+TA7)
5108 fadd.d SINA3(%pc),%fp3 # A3+T(A5+TA7)
5111 fmul.x %fp3,%fp1 # T(A3+T(A5+TA7))
5114 fadd.x SINA1(%pc),%fp1 # A1+T(A3+T(A5+TA7))
6785 # p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) #
6788 # and A5 are single precision; A2 and A3 are double #
6796 # [ S*(A1 + S*(A3 + S*A5)) ] #
7152 #-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))
7154 #--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))]
[all …]
Dfpsp.S5184 #--R' + R'*S*( [A1+T(A3+T(A5+TA7))] + [S(A2+T(A4+TA6))])
5223 fadd.x %fp2,%fp1 # [A1+T(A3+T(A5+TA7))]+[S(A2+T(A4+TA6))]
5418 fadd.d SINA5(%pc),%fp1 # A5+S(A6+SA7)
5421 fmul.x %fp0,%fp1 # S(A5+S(A6+SA7))
5425 fadd.d SINA4(%pc),%fp1 # A4+S(A5+S(A6+SA7))
5493 fadd.d SINA5(%pc),%fp2 # A5+S(A6+SA7)
5496 fmul.x %fp0,%fp2 # S(A5+S(A6+SA7))
5499 fadd.d SINA4(%pc),%fp2 # A4+S(A5+S(A6+SA7))
7019 # p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6))))) #
7021 # are made as "short" as possible: A1 (which is 1/2), A5 #
[all …]
/arch/arm64/boot/dts/qcom/
Dmsm8916-samsung-a2015-common.dtsi78 * NOTE: A5 connects GPIO 76 to a reglator powering the motor
/arch/arm/boot/dts/aspeed/
Daspeed-bmc-tyan-s8036.dts403 /*A5*/ "",
Daspeed-bmc-tyan-s7106.dts449 /*A5*/ "",