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Searched refs:L1_CACHE_BYTES (Results 1 – 25 of 96) sorted by relevance

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/arch/sh/mm/
Dflush-sh4.c19 v = aligned_start & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region()
20 end = (aligned_start + size + L1_CACHE_BYTES-1) in sh4__flush_wback_region()
21 & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region()
22 cnt = (end - v) / L1_CACHE_BYTES; in sh4__flush_wback_region()
25 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
26 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
27 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
28 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
29 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
30 __ocbwb(v); v += L1_CACHE_BYTES; in sh4__flush_wback_region()
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Dcache-sh2.c23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_wback_region()
25 & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
26 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh2__flush_wback_region()
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
45 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_purge_region()
46 & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
48 for (v = begin; v < end; v+=L1_CACHE_BYTES) in sh2__flush_purge_region()
75 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_invalidate_region()
76 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_invalidate_region()
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Dcache-sh2a.c57 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
58 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_wback_region()
59 & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
70 for (v = begin; v < end; v += L1_CACHE_BYTES) { in sh2a__flush_wback_region()
78 for (v = begin; v < end; v += L1_CACHE_BYTES) in sh2a__flush_wback_region()
97 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_purge_region()
98 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_purge_region()
99 & ~(L1_CACHE_BYTES-1); in sh2a__flush_purge_region()
104 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh2a__flush_purge_region()
127 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_invalidate_region()
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Dcache-sh3.c38 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh3__flush_wback_region()
39 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh3__flush_wback_region()
40 & ~(L1_CACHE_BYTES-1); in sh3__flush_wback_region()
42 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh3__flush_wback_region()
76 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh3__flush_purge_region()
77 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh3__flush_purge_region()
78 & ~(L1_CACHE_BYTES-1); in sh3__flush_purge_region()
80 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh3__flush_purge_region()
/arch/csky/mm/
Dcachev2.c26 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in icache_inv_range()
28 for (; i < end; i += L1_CACHE_BYTES) in icache_inv_range()
49 unsigned long i = param->start & ~(L1_CACHE_BYTES - 1); in local_icache_inv_range()
54 for (; i < param->end; i += L1_CACHE_BYTES) in local_icache_inv_range()
81 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in dcache_wb_range()
83 for (; i < end; i += L1_CACHE_BYTES) in dcache_wb_range()
97 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in dma_wbinv_range()
99 for (; i < end; i += L1_CACHE_BYTES) in dma_wbinv_range()
106 unsigned long i = start & ~(L1_CACHE_BYTES - 1); in dma_inv_range()
108 for (; i < end; i += L1_CACHE_BYTES) in dma_inv_range()
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/arch/microblaze/include/asm/
Dcache.h17 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
19 #define SMP_CACHE_BYTES L1_CACHE_BYTES
22 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
24 #define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
/arch/hexagon/include/asm/
Dcache.h13 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
15 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
17 #define __cacheline_aligned __aligned(L1_CACHE_BYTES)
18 #define ____cacheline_aligned __aligned(L1_CACHE_BYTES)
/arch/arm/lib/
Dcopy_page.S14 #define COPY_COUNT (PAGE_SZ / (2 * L1_CACHE_BYTES) PLD( -1 ))
27 PLD( pld [r1, #L1_CACHE_BYTES] )
30 1: PLD( pld [r1, #2 * L1_CACHE_BYTES])
31 PLD( pld [r1, #3 * L1_CACHE_BYTES])
33 .rept (2 * L1_CACHE_BYTES / 16 - 1)
/arch/alpha/include/asm/
Dcache.h11 # define L1_CACHE_BYTES 64 macro
17 # define L1_CACHE_BYTES 32 macro
21 #define SMP_CACHE_BYTES L1_CACHE_BYTES
/arch/arc/kernel/
Dvmlinux.lds.S62 INIT_TEXT_SECTION(L1_CACHE_BYTES)
67 INIT_SETUP(L1_CACHE_BYTES)
78 PERCPU_SECTION(L1_CACHE_BYTES)
95 EXCEPTION_TABLE(L1_CACHE_BYTES)
105 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
/arch/powerpc/include/asm/
Dcache.h30 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
32 #define SMP_CACHE_BYTES L1_CACHE_BYTES
37 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
89 return L1_CACHE_BYTES; in l1_dcache_bytes()
99 return L1_CACHE_BYTES; in l1_icache_bytes()
Dpage_32.h44 WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1)); in clear_page()
46 for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES) in clear_page()
/arch/csky/kernel/
Dvmlinux.lds.S49 PERCPU_SECTION(L1_CACHE_BYTES)
55 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
106 EXCEPTION_TABLE(L1_CACHE_BYTES)
107 BSS_SECTION(L1_CACHE_BYTES, PAGE_SIZE, L1_CACHE_BYTES)
/arch/xtensa/include/asm/
Dcache.h17 #define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE macro
18 #define SMP_CACHE_BYTES L1_CACHE_BYTES
32 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/arch/nios2/kernel/
Dvmlinux.lds.S41 EXCEPTION_TABLE(L1_CACHE_BYTES)
47 PERCPU_SECTION(L1_CACHE_BYTES)
52 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
/arch/m68k/include/asm/
Dcache.h10 #define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT) macro
12 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/arch/arm/include/asm/
Dcache.h9 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
18 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/arch/ia64/include/asm/
Dcache.h13 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
17 # define SMP_CACHE_BYTES L1_CACHE_BYTES
/arch/riscv/include/asm/
Dcache.h12 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
15 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/arch/nios2/include/asm/
Dcache.h19 #define L1_CACHE_BYTES NIOS2_ICACHE_LINE_SIZE macro
21 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/arch/sh/include/asm/
Dcache.h15 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
21 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/arch/csky/include/asm/
Dcache.h9 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
11 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/arch/x86/entry/
Dentry.S34 .align L1_CACHE_BYTES, 0xcc
39 .align L1_CACHE_BYTES, 0xcc
/arch/riscv/kernel/
Dvmlinux-xip.lds.S51 RO_DATA(L1_CACHE_BYTES)
75 RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
121 PERCPU_SECTION(L1_CACHE_BYTES)
/arch/powerpc/lib/
Dchecksum_32.S120 CACHELINE_BYTES = L1_CACHE_BYTES
122 CACHELINE_MASK = (L1_CACHE_BYTES-1)
195 #if L1_CACHE_BYTES >= 32
197 #if L1_CACHE_BYTES >= 64
200 #if L1_CACHE_BYTES >= 128
255 #if L1_CACHE_BYTES >= 32
257 #if L1_CACHE_BYTES >= 64
260 #if L1_CACHE_BYTES >= 128

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